Quantum circuit decomposition by integer programming
Techniques and a system for quantum circuit decomposition by integer programming are provided. In one example, a system includes a quantum circuit decomposition component and a simulation component. The quantum circuit decomposition component generates graphical data for a quantum circuit that is indicative of a graphical representation of the quantum circuit. The graphical representation is formatted as a hypergraph. The simulation component simulates the quantum circuit based on the graphical data associated with the hypergraph.
1. A system, comprising:
a memory that stores computer executable components;
a processor that executes computer executable components stored in the memory, wherein the computer executable components comprise:
a quantum circuit decomposition component that generates graphical data for a quantum circuit that is indicative of a graphical representation of the quantum circuit, wherein the graphical representation is formatted as a hypergraph, wherein the hypergraph comprises an output node that indicates which wires of the quantum circuit are open to construct input data for integer programming; and
a simulation component that simulates the quantum circuit based on the graphical data associated with the hypergraph.
2. The system of claim 1 , wherein the quantum circuit decomposition component generates a set of sub-circuits for the quantum circuit based on the graphical data associated with the hypergraph.
3. The system of claim 2 , wherein the simulation component simulates the set of sub-circuits.
4. The system of claim 1 , wherein a node of the hypergraph represents a tensor associated with the quantum circuit.
5. The system of claim 4 , wherein a hyperedge of the hypergraph represents an index label for the tensor.
6. The system of claim 4 , wherein the quantum circuit decomposition component partitions the hypergraph based on a computation sequence for a simulation process associated with the quantum circuit.
7. The system of claim 1 , wherein the quantum circuit decomposition component performs integer programming optimization to generate a set of sub-circuits for the quantum circuit.
8. The system of claim 1 , wherein the simulation component determines a memory requirement for a simulation process associated with the quantum circuit based on analysis of the graphical data.
9. The system of claim 1 , wherein the simulation component simulates a first portion of the hypergraph and a second portion of the hypergraph in parallel in response to a determination that the first portion of the hypergraph and the second portion of the hypergraph are included in a corresponding computation sequence for a simulation process associated with the quantum circuit.
10. The system of claim 1 , wherein the simulation component simulates the quantum circuit based on the graphical data associated with the hypergraph to reduce an amount of processing for a simulation process associated with the quantum circuit.
11. A computer-implemented method, comprising:
generating, by a system operatively coupled to a processor, graphical data for a quantum circuit indicative of a graphical representation of the quantum circuit that is formatted as a hypergraph, wherein the hypergraph comprises an output node that indicates which wires of the quantum circuit are open to construct input data for integer programming;
generating, by the system, a set of sub-circuits for the quantum circuit based on the hypergraph; and
simulating, by the system, the set of sub-circuits for the quantum circuit.
12. The computer-implemented method of claim 11 , wherein the generating the graphical data comprises converting tensor data indicative of information for a tensor network representative of the quantum circuit into the graphical data.
13. The computer-implemented method of claim 11 , wherein the generating the graphical data comprises representing a gate of the quantum circuit as a node in the hypergraph.
14. The computer-implemented method of claim 11 , wherein the generating the graphical data comprises representing a connection of the quantum circuit as a hyperedge in the hypergraph.
15. The computer-implemented method of claim 11 , wherein the generating the set of sub-circuits comprises performing an integer programming process associated with the graphical data.
16. The computer-implemented method of claim 11 , wherein the generating the set of sub-circuits comprises reducing an amount of processing for a simulation process associated with the quantum circuit.
17. A computer program product for quantum computing simulation, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:
generate, by the processor, graphical data for a quantum circuit indicative of a graphical representation of the quantum circuit that is formatted as a hypergraph, wherein the hypergraph comprises an output node that indicates which wires of the quantum circuit are open to construct input data for integer programming;
generate, by the processor, a set of sub-circuits for the quantum circuit based on the hypergraph; and
simulate, by the processor, the set of sub-circuits for the quantum circuit.
18. The computer program product of claim 17 , wherein the program instructions are further executable by the processor to cause the processor to:
convert, by the processor, tensor data indicative of information for a tensor network representative of the quantum circuit into the graphical data.
19. The computer program product of claim 17 , wherein the program instructions are further executable by the processor to cause the processor to:
configure, by the processor, a node in the hypergraph to represent a gate of the quantum circuit.
20. The computer program product of claim 17 , wherein the program instructions are further executable by the processor to cause the processor to:
configure, by the processor, a hyperedge in the hypergraph to represent a connection of the quantum circuit.
21. A system, comprising:
a memory that stores computer executable components;
a processor that executes computer executable components stored in the memory, wherein the computer executable components comprise:
a quantum circuit decomposition component that generates graphical data for a quantum circuit and generates a set of sub-circuits for the quantum circuit based on the graphical data, wherein the graphical data is indicative of a graphical representation of the quantum circuit that is formatted as a hypergraph, wherein the hypergraph comprises an output node that indicates which wires of the quantum circuit are open to construct input data for integer programming; and
a simulation component that simulates the set of sub-circuits associated with the hypergraph.
22. The system of claim 21 , wherein a node of the hypergraph represents a gate associated with the quantum circuit.
23. The system of claim 21 , wherein a hyperedge of the hypergraph represents a connection associated with the quantum circuit.
24. A computer program product for quantum computing simulation, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:
generate, by the processor, graphical data for a quantum circuit that is indicative of a graphical representation of the quantum circuit, wherein the graphical representation is formatted as a hypergraph, wherein the hypergraph comprises an output node that indicates which wires of the quantum circuit are open to construct input data for integer programming; and
simulate, by the processor, the quantum circuit based on the graphical data associated with the hypergraph.
25. The computer program product of claim 24 , wherein the program instructions are further executable by the processor to cause the processor to:
generate, by the processor, a set of sub-circuits for the quantum circuit based on the graphical data associated with the hypergraph.