Imprint management for memory
Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
1. A method, comprising:
writing a first set of logic states to a subset of memory cells within a memory array before a deactivation of the memory array;
writing a second set of logic states to the subset of memory cells after a reactivation of the memory array;
reading the subset of memory cells to obtain a third set of logic states that are based at least in part on writing the second set of logic states;
determining a first quantity of errors for the subset of memory cells based at least in part on comparing the third set of logic states to the first set of logic states; and
performing a recovery operation on the memory array when the first quantity of errors satisfies a threshold.
2. The method of claim 1 , further comprising:
performing, before the deactivation of the memory array, a wear-leveling procedure for the memory array, wherein the wear-leveling procedure makes the subset of memory cells available for storing the first set of logic states.
3. The method of claim 2 , wherein:
the memory array comprises a plurality of word lines; and
the memory cells of the subset are coupled with one or more word lines of the plurality, the one or more word lines made available based at least in part on the wear-leveling procedure.
4. The method of claim 1 , wherein:
writing the first set of logic states comprises writing a first logic state to a first portion of the subset of memory cells and a second logic state to a second portion of the subset of memory cells; and
writing the second set of logic states comprises writing a same logic state to each memory cell of the subset.
5. The method of claim 4 , wherein reading the subset of memory cells to obtain the third set of logic states is based at least in part on a first reference voltage, further comprising:
reading, based at least in part on a second reference voltage that is different from the first reference voltage, the subset of memory cells to obtain a fourth set of logic states that are based at least in part on writing the second set of logic states;
determining a second quantity of errors for the subset of memory cells based at least in part on comparing the fourth set of logic states to the first set of logic states; and
performing the recovery operation at the memory array based at least in part on a difference between the first quantity of errors and the second quantity of errors.
6. The method of claim 5 , further comprising:
reading the subset of memory cells, before the deactivation of the memory array, based at least in part on a third reference voltage, wherein the first reference voltage and the second reference voltage are both less than or both greater than the third reference voltage.
7. The method of claim 4 , wherein:
reading the subset of memory cells to obtain the third set of logic states comprises using a first reference voltage; and
the threshold is based at least in part on an expected quantity of errors associated with reading at the first reference voltage.