Deuterium-based passivation of non-planar transistor interfaces
Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides. Such interfaces are common locations of trap sites that may include impurities, incomplete bonds dangling bonds, and broken bonds, for example, and thus such interfaces can benefit from deuterium-based passivation to improve the performance and reliability of the transistor.
1. An integrated circuit comprising:
a fin structure comprising an upper region, a lower region, and a middle region between the upper and lower regions, wherein the fin structure further includes a sub-region below the lower region, the sub-region having sides that are in contact with regions ofinsulator material; and
a gate structure wrapped around the middle region of the fin structure and not wrapped around the lower region or the upper region of the fin structure, wherein the gate structure includes a gate electrode and a gate dielectric, the gate dielectric wrapped around the middle region of the fin structure, and the gate electrode wrapped around the gate dielectric;
wherein deuterium is present along the entire interface between the gate dielectric and the middle region of the fin structure, and wherein deuterium is present at side interfaces between the sub-region of the fin and the regions of insulator material.
2. The integrated circuit of claim 1 , wherein at least the middle region of the fin structure comprises one or both of silicon and germanium.
3. The integrated circuit of claim 1 , wherein the upper and lower regions have a first material composition, and the middle region has a second material composition that is different from the first material composition.
4. A computing system comprising the integrated circuit of claim 1 .
5. An integrated circuit comprising:
a substrate;
a fin structure extending from the substrate, wherein the fin structure comprises an upper region, a lower region, a middle region between the upper and lower regions, and a sub-region beneath the lower region; and
a gate structure wrapped around the middle region of the fin structure, wherein the gate structure includes a gate electrode and a gate dielectric, the gate dielectric wrapped around the middle region of the fin structure, and the gate electrode wrapped around the gate dielectric;
wherein deuterium is present along the entire interface between the gate dielectric and the middle region of the fin structure;
wherein sides of the sub-region are in contact with regions of insulator material; and
wherein deuterium is present at side interfaces between the sub-region of the fin and the regions of insulator material.
6. The integrated circuit of claim 5 , wherein the upper region is one of a source or drain region of a vertical transistor, and the lower region is the other one of the source or drain region of the vertical transistor.
7. The integrated circuit of claim 1 , wherein hydrogen is also present along the entire interface between the gate dielectric and the middle region of the fin structure.
8. The integrated circuit of claim 1 , wherein deuterium is present within the gate dielectric.
9. The integrated circuit of claim 5 , wherein hydrogen is also present along the entire interface between the gate dielectric and the middle region of the fin structure.
10. The integrated circuit of claim 5 , wherein at least the middle region of the fin structure comprises one or both of silicon and germanium.
11. The integrated circuit of claim 5 , wherein deuterium is present within the gate dielectric.
12. An integrated circuit comprising:
a fin structure comprising an upper region, a lower region, a middle region between the upper and lower regions, and a sub-region beneath the lower region; and
a gate structure wrapped around the middle region of the fin structure and not wrapped around the lower region or the upper region of the fin structure, wherein the gate structure includes a gate electrode and a gate dielectric, the gate dielectric wrapped around the middle region of the fin structure, and the gate electrode wrapped around the gate dielectric;
wherein deuterium is present along the interface between the gate dielectric and the middle region of the fin structure; and
wherein deuterium is present at side interfaces between the sub-region of the fin and regions of insulator material in contact with the sub-region of the fin.
13. The integrated circuit of claim 12 , wherein deuterium is present within the gate dielectric.
14. The integrated circuit of claim 12 , wherein the upper region is one of a source or drain region of a vertical transistor, and the lower region is the other one of the source or drain region of the vertical transistor.
15. The integrated circuit of claim 12 , wherein hydrogen is also present along the interface between the gate dielectric and the middle region of the fin structure.
16. The integrated circuit of claim 12 , wherein at least the middle region of the fin structure comprises one or both of silicon and germanium.
17. The integrated circuit of claim 12 , further comprising a substrate, wherein the fin structure is compositionally different than the substrate.