Polar code encoding/decoding method and encoding/decoding apparatus
Embodiments of polar encoding/decoding methods and apparatuses are described. CRC encoding is performed on an information block to obtain a CRC encoded block with a length of B, where a CRC length is Lcrc, an information block length is K, and B=K+Lcrc. The CRC encoded block is interleaved. Lpc CRC bits in the interleaved encoded block are located between bits of the information block. Each CRC bit of the Lpc CRC bits is located after all bits checked by using the CRC bit. Lpc is an integer greater than 0 and less than Lcrc. The interleaved encoded block is mapped to information bits. A frozen bit is set to an agreed fixed value. Polar encoding is performed on the information bits and the frozen bit to obtain a polar encoded codeword to improve performance of a CA-polar code.
1. A polar encoding method, comprising:
performing, by a processor, cyclic redundancy check (CRC) encoding on an information block to obtain a CRC encoded block with a length of B, wherein a CRC length is Lcrc, an information block length is K, and B=K+Lcrc;
interleaving, by the processor, the CRC encoded block, wherein Lpc CRC bits in an interleaved encoded block are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked by using the CRC bit, and Lpc is an integer greater than 0 and less than Lcrc;
mapping, by the processor, the interleaved encoded block to positions of information bits,
setting, by the processor, a frozen bit to an agreed fixed value, and
performing, by the processor, polar encoding on the information bits and the frozen bit to obtain a polar encoded codeword, wherein positions of the information bits and the frozen bit are obtained based on reliabilities of polarized channels.
2. The method according to claim 1 , wherein the interleaving the CRC encoded block comprises:
interleaving the CRC encoded block by using an interleaving sequence π=[π 1 , π 2 , . . . , π n ], and permuting a CRC encoded bit sequence [b1, b2, . . . , bn] into bπ 1 , bπ 2 , . . . , bπ n , wherein n is an integer greater than 0 and less than or equal to B, and a value of π n represents a bit position sequence number that is of an n th bit of the interleaved encoded block and that is in the CRC encoded block before the interleaving is performed.
3. The method according to claim 1 , wherein Lpc meets the following condition:
L pc ≤L crc −log 2 T +log 2 FAR,
and wherein
T represents a pre-agreed quantity of candidate paths for selecting a decoding result through CRC check during decoding, and FAR represents a false alarm rate upper limit specified in a communications system.
4. The method according to claim 1 , wherein Lcrc and Lpc meet the following relationship: Lcrc−Lpc=10; or Lcrc−Lpc=18.
5. The method according to claim 1 , wherein Lpc=1 and Lcrc=11; Lpc=2 and Lcrc=12; Lpc=4 and Lcrc=14; Lpc=6 and Lcrc=16; or Lpc=8 and Lcrc=18.
6. The method according to claim 1 , wherein Lpc=1 and Lcrc=19; Lpc=2 and Lcrc=20; Lpc=4 and Lcrc=22; Lpc=6 and Lcrc=24; or Lpc=8 and Lcrc=26.
7. An encoding apparatus, comprising:
a memory, configured to store a program; and
a processor, configured to execute the program stored in the memory, wherein when the program is executed, the processor is configured to: perform cyclic redundancy check CRC encoding on an information block to obtain a CRC encoded block with a length of B, wherein a CRC length is Lcrc, an information block length is K, and B=K+Lcrc; interleave the CRC encoded block, wherein Lpc CRC bits in an interleaved encoded block are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked by using the CRC bit, and Lpc is an integer greater than 0 and less than Lcrc; map the interleaved encoded block to information bits, set a frozen bit to an agreed fixed value, and perform polar encoding on the information bits and the frozen bit to obtain a polar encoded codeword, wherein positions of the information bits and the frozen bit are obtained based on reliabilities of polarized channels.
8. The apparatus according to claim 7 , wherein Lpc meets the following condition:
L pc ≤L crc −log 2 T +log 2 FAR,
and wherein
T represents a pre-agreed quantity of candidate paths for selecting a decoding result through CRC check during decoding, and FAR represents a false alarm rate upper limit specified in a communications system.
9. The apparatus according to claim 7 , wherein Lcrc and Lpc meet the following relationship: Lcrc−Lpc=10; or Lcrc−Lpc=18.
10. The apparatus according to claim 7 , wherein Lpc=1 and Lcrc=11; Lpc=2 and Lcrc=12; Lpc=4 and Lcrc=14; Lpc=6 and Lcrc=16; or Lpc=8 and Lcrc=18.
11. The apparatus according to claim 7 , wherein Lpc=1 and Lcrc=19; Lpc=2 and Lcrc=20; Lpc=4 and Lcrc=22; Lpc=6 and Lcrc=24; or Lpc=8 and Lcrc=26.
12. A polar decoding method, comprising:
receiving to-be-decoded bits;
obtaining, by a processor, positions of information bits and a frozen bit in the to-be-decoded bits, wherein the information bits comprise K bits of an information block and Lcrc cyclic redundancy check CRC bits, Lpc CRC bits are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked by using the CRC bit, and Lpc is an integer greater than 0 and less than Lcrc;
decoding, by the processor, the to-be-decoded bits, based on the positions of the information block and the CRC bits.
13. The method according to claim 12 , wherein Lpc, Lcrc, T, and a false alarm rate FAR upper limit that is specified in a communications system meet the following relationship:
L pc ≤L crc −log 2 T +log 2 FAR,
T represents a pre-agreed quantity of candidate paths for selecting a decoding result through CRC check during decoding, and FAR represents a false alarm rate upper limit specified in a communications system.
14. The method according to claims 12 , wherein Lcrc and Lpc meet the following relationship: Lcrc−Lpc=10; or Lcrc−Lpc=18.
15. A decoding apparatus, comprising:
a memory; and
a processor coupled to the memory, wherein the processor is configured to: receive to-be-decoded bits;
obtain positions of information bits and a frozen bit in the to-be-decoded bits, wherein the information bits comprise K bits of an information block and Lcrc cyclic redundancy check CRC bits, Lpc CRC bits are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked by using the CRC bit, and Lpc is an integer greater than 0 and less than Lcrc;
decode the to-be-decoded bits, based on the positions of the information block and the CRC bits.
16. The apparatus according to claim 15 , wherein Lpc, Lcrc, T, and a false alarm rate FAR upper limit that is specified in a communications system meet the following relationship:
L pc ≤L crc −log 2 T +log 2 FAR,
T represents a pre-agreed quantity of candidate paths for selecting a decoding result through CRC check during decoding, and FAR represents a false alarm rate upper limit specified in a communications system.
17. The apparatus according to claim 15 , wherein Lcrc and Lpc meet the following relationship: Lcrc−Lpc=10; or Lcrc−Lpc=18.