Wafer-scale membrane release laminates, devices and processes

1. A bolometric detector semiconductor processing laminate construct, comprising:

a handling substrate including a photoresist material on a first surface thereof;

a semiconductor wafer having a circuit pattern on a first surface and a second surface to be processed; and

a temporary adhesive layer temporarily bonding the first surface of the semiconductor wafer to the first surface of the handling substrate including the photoresist material; wherein the semiconductor processing laminate construct includes the handling substrate including the photoresist material on the first surface thereof, a semiconductor on insulator wafer device and the temporary adhesive layer with the semiconductor on insulator wafer device includes the semiconductor wafer having said circuit pattern on the first surface and the second surface and insulator material to be processed on the second surface of the semiconductor wafer; a wafer assembly micromachined with a silicon device layer that includes the circuit pattern thereon, a buried oxide layer and a silicon frame region whereby the buried oxide layer and silicon frame region make up an insulator layer whereby the temporary adhesive layer temporarily bonds the first surface of the semiconductor wafer to the first surface of the handling substrate thus reducing capillary pressure on a silicon wafer by an amount approximately proportional to an existing solvent surface tension and inversely proportional to a distance between the handling substrate and thickness of a photoresist material section positioned in between the handling substrate and the semiconductor wafer;

means for applying and patterning photoresist material onto a side of the handling substrate with a laminated film; means for etching of the laminated film, application of a temporary adhesive to the patterned photoresist material; and

means for wafer-scale bonding of the patterned photoresist material coated handling substrate to a semiconductor on insulator handle wafer substrate.

2. The semiconductor processing laminate construct of claim 1 , wherein the handling substrate includes a section of the photoresist material and a section of exposed substrate of the first surface thereof.

3. The semiconductor processing laminate construct of claim 2 , wherein the temporary adhesive is positioned in contact with the section of exposed substrate.

4. The semiconductor processing laminate construct of claim 1 , wherein the photoresist material is positioned between the first surface of the handling substrate and the first surface of the semiconductor wafer.

5. The semiconductor processing laminate construct of claim 1 , wherein the handling substrate includes a section of the photoresist material and a section of exposed substrate of the first surface thereof, the temporary adhesive is positioned in contact with the section of exposed substrate and the photoresist material is positioned between the first surface of the handling substrate and the first surface of the semiconductor wafer.

6. The semiconductor processing laminate construct of claim 1 , wherein the handling substrate includes a plurality of sections of the photoresist material and the sections of photoresist material are of substantially uniform thickness relative to the first surface of the handling substrate.

7. The semiconductor processing laminate construct of claim 1 , wherein the handling substrate is an aluminum coated sapphire substrate.

8. The semiconductor processing laminate construct of claim 1 , wherein the photoresist material is SU-8.