Thin film transistor with small storage capacitor with metal oxide switch

1. A sub-pixel circuit for a display, the sub-pixel circuit comprising:

a driving TFT;

at least one switching TFT wherein the at least one switching TFT is an oxide TFT; and

at least one storage capacitor, wherein the storage capacitor is formed by overlapping a gate metal and a source metal of the driving TFT, and wherein the storage capacitor has a capacitance between about 1 fF and about 55 fF.

2. The sub-pixel circuit of claim 1 , wherein the driving TFT is an oxide TFT.

3. The sub-pixel circuit of claim 1 , wherein the driving TFT is a polysilicon TFT.

4. The sub-pixel circuit of claim 1 , wherein the at least one switching TFT further comprises:

a gate insulating layer thickness of between about 100 nm and about 200 nm;

a TFT channel length of between about 0.5 μm and 3 μm; and

a TFT channel width of between about 1 μm and about 4 μm.

5. The sub-pixel circuit of claim 4 , wherein the at least one switching TFT further comprises:

a TFT leakage current less than about 1E-12 (A).

6. A sub-pixel circuit formed in a stack, the sub-pixel circuit comprising: a driving TFT comprising: a source disposed on a top surface of the stack;

a drain on the top surface of the stack; and a conductive channel formed in the stack, the conductive channel having a first end and a second end, wherein the first end is electrically coupled to the source and the second end is electrically coupled to the drain; at least one switching TFT; a storage capacitor wherein the storage capacitor is inside the driving TFT disposed above the conductive channel and below the top surface; and a second storage capacitor formed below the switching TFT.

7. The sub-pixel circuit of claim 6 wherein the stack further comprises:

a first layer forming a first buffer layer;

a second layer formed from a gate insulating material;

a third layer forming a first inter layer dielectric;

a fourth layer forming a second buffer layer; and

a fifth layer forming a second inter layer dielectric, wherein the at least one switching TFT is an oxide TFT and the at least one switching TFT does not extend into the fourth layer.

8. The sub-pixel circuit of claim 6 , wherein the driving TFT is an oxide TFT.

9. The sub-pixel circuit of claim 6 , wherein the driving TFT is a polysilicon TFT.

10. The sub-pixel circuit of claim 6 , wherein the storage capacitor is formed by overlapping a gate metal and a source metal of the driving TFT.

11. The sub-pixel circuit of claim 7 , wherein the storage capacitor further comprises:

a gate insulator and the storage capacitor does not extend into the fourth layer.

12. The sub-pixel circuit of claim 7 , wherein the storage capacitor extends below the fourth layer and the conductive channel is in the second layer.

13. The sub-pixel circuit of claim 7 , further comprising:

a light shield disposed below the switching TFT.

14. The sub-pixel circuit of claim 6 , further comprising: a third storage capacitor formed below the driving TFT.

15. A display comprising:

a plurality of pixels, the pixels comprising:

a plurality of sub-pixels, each sub-pixel of the plurality of pixels comprising:

an OLED area; and

a sub-pixel circuit, the sub-pixel circuit comprising:

a driving TFT;

at least one switching TFT, wherein the at least one switching TFT is an oxide TFT; and

at least one storage capacitor formed within the driving TFT, wherein the storage capacitor has a capacitance between about 1 fF and about 55 fF and is formed by overlapping a gate metal and a source metal of the driving TFT.

16. A display comprising:

a plurality of pixels, the pixels comprising:

a plurality of sub-pixels, each sub-pixel of the plurality of pixels comprising:

an OLED area; and

a sub-pixel circuit, the sub-pixel circuit comprising:

a driving TFT;

at least one switching TFT, wherein the at least one switching TFT is an oxide TFT;

a first storage capacitor formed within the driving TFT, wherein the storage capacitor has a capacitance between about 1 fF and about 55 fF and is formed by overlapping a gate metal and a source metal of the driving TFT; and

a second storage capacitor formed below the at least one switching TFT.