System and method for non-speculative reordering of load accesses
Methods and systems for maintaining validity of a memory model in a multiple core computer system are described. A first core prevents a store instruction from being performed by another core until a condition is met which enables reordered instructions to validly execute.
1. A computer system comprising:
multiple processor cores;
a store buffer associated with and operatively coupled to each core for placing store instructions when they are committed and before they are performed in a memory system;
at least one local cache memory associated with and operatively coupled to each core for storing one or more cache lines accessible only by an associated core;
a shared memory, the shared memory being operatively coupled to the local cache memories and accessible by the multiple processor cores, the shared memory being capable of storing a plurality of cache lines or memory blocks; and
a coherence mechanism to keep the multiple processor cores and the shared memory coherent;
wherein a first core uses the coherence mechanism to prevent a store in the store buffer of another core from being performed in the memory system without squashing the store, until a condition is met which enables reordered instructions to validly execute.
2. The computer system of claim 1 wherein the first core prevents the store in the store buffer of the another core from being performed in the memory system until at least one load instruction is performed in the first core.
3. The computer system of claim 2 wherein a load instruction that performs out-of-order with respect to older, in program order, load instructions in a same core, prevents a store, to a same cache line address as the load in the store buffer of another core from being performed in the memory system, until at least a time when at least one older load, in program order, in the first core is performed.
4. The computer system of claim 3 wherein the load instruction that performs out-of-order with respect to older, in program order, load instructions in the same core, prevents the store, to the same cache line address as the load, in the store buffer of another core from being performed, by withholding an acknowledgment to invalidation that is sent when said store attempts to be performed in the memory system, and returning said acknowledgement after at least one older load, in program order, in the first core is performed.
5. The computer system of claim 4 wherein load queue entries are augmented with an S (“Seen”) bit and wherein the S bit of a load queue entry is set if a load in said entry performed out of order with respect to older, in program order, loads in the same core, and a load queue entry is matched by an invalidation to the same cache line address, and the load is the youngest, in program order, load on the said cache line address; and wherein a load queue entry with a set S bit returns the acknowledgment to said invalidation when at least one older load, in program order, than the load of said load queue entry, is performed.
6. The computer system of claim 5 wherein a separate table keeps a correspondence of S (“Seen”) bits and loads that perform out of order with respect to older, in program order, loads in the same core.
7. A method for maintaining validity of a memory model in a multiple core computer system, the method comprising:
preventing, by a first core, a store in a store buffer of another core from being performed in a memory system without squashing the store, until a condition is met which enables reordered instructions to validly execute,
wherein the preventing comprises using a coherence mechanism.
8. The method of claim 7 wherein the first core prevents a store in the store buffer of the another core from being performed in the memory system until at least one load instruction is performed in the first core.
9. The method of claim 8 , wherein a load instruction that performs out-of-order with respect to older, in program order, load instructions in the same core, prevents a store, to a same cache line address as the load instruction in the store buffer of another core from being performed in the memory system, until at least a time when at least one older load, in program order, in the first core is performed.
10. The method of claim 9 , wherein the step of preventing the store further comprises:
withholding an acknowledgment to an invalidation that is sent when said store attempts to be performed in the memory system, and
returning said acknowledgement after at least one older load, in program order, in the first core is performed.
11. The method of claim 10 , wherein load queue entries are augmented with an S (“Seen”) bit and wherein the S bit of a load queue entry is set if the load in said entry performed out of order with respect to older, in program order, loads in the same core, and the load queue entry is matched by an invalidation to the same cache line address, and the load is the youngest, in program order, load on the said cache line address; and wherein a load queue entry with a set S bit returns the acknowledgment to said invalidation when at least one older load, in program order, than the load of said load queue entry, is performed.
12. The method of claim 11 , wherein a separate table keeps a correspondence of S (“Seen”) bits and loads that perform out of order with respect to older, in program order, loads in the same core.
13. The computer system of claim 1 , wherein the coherence mechanism comprises one or both of delaying acknowledgement of an invalidation and repeatedly negative-acknowledging the invalidation.
14. The method of claim 1 , wherein the coherence mechanism comprises one or both of delaying acknowledgement of an invalidation and repeatedly negative-acknowledging the invalidation.