IP Library › Granted Patent US 11,107,405
Granted Patent B2
US 11,107,405 · App. 16/305,426 · Granted Aug 31, 2021

Pixel compensation circuit unit, pixel circuit and display device

Inventor: Yuhsiung Feng (Beijing, CN)
Assignees: BOE TECHNOLOGY GROUP CO., LTD.; CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
G09G3/3258G09G2300/0426G09G2310/061
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Quick Facts
Patent No.
US 11,107,405
App. No.
16/305,426
Granted
Aug 31, 2021
Kind
B2
Abstract

A pixel compensation circuit unit, a pixel circuit, and a display device are provided in the disclosure. The pixel compensation circuit unit may include a reset power supply line, a reset control circuit, a bridge circuit, and at least two pixel compensation circuits. The at least two pixel compensation circuits are coupled to the reset power supply line, respectively; the reset control circuit is coupled to the reset power supply line and the bridge circuit, respectively; and the at least two pixel compensation circuits are coupled by the bridge circuit. A plurality of pixel compensation circuits may share one reset power supply line, thereby reducing the number of reset power supply lines and simplifying the structure of the pixel compensation circuit unit.

Claims (47)

1. A pixel compensation circuit unit comprising: a reset power supply line, a reset control circuit, a bridge circuit, and at least two pixel compensation circuits, wherein

the at least two pixel compensation circuits are coupled to the reset power supply line, respectively;

a first terminal of the reset control circuit is coupled to the reset power supply line, and a second terminal of the reset control circuit is coupled to the bridge circuit; and

the at least two pixel compensation circuits are coupled to each other by the bridge circuit.

2. The pixel compensation circuit unit according to claim 1 , wherein

the at least two pixel compensation circuits comprise a first pixel compensation circuit and a second pixel compensation circuit;

the bridge circuit is coupled to a first node, and the first pixel compensation circuit is coupled to the first node; and

the bridge circuit is coupled to a second node, and the second pixel compensation circuit is coupled to the second node.

3. The pixel compensation circuit unit according to claim 2 , wherein

the bridge circuit comprises a first switch;

a control electrode of the first switch is coupled to a first control power supply line, a first electrode of the first switch is coupled to the first node, and a second electrode of the first switch is coupled to the second node; and

the reset control circuit is couple to the first node.

4. The pixel compensation circuit unit according to claim 2 , wherein

the bridge circuit comprises a first switch;

a control electrode of the first switch is coupled to a first control power supply line, a first electrode of the first switch is coupled to the first node, and a second electrode of the first switch is coupled to the second node; and

the reset control circuit is couple to the second node.

5. The pixel compensation circuit unit according to claim 2 , wherein

the bridge circuit comprises a second switch and a third switch;

a control electrode of the second switch is couple to a first control power supply line, a first electrode of the second switch is coupled to the first node, and a second electrode of the second switch is coupled to a third node;

a control electrode of the third switch is couple to the first control power supply line, a first electrode of the third switch is coupled to the third node, and a second electrode of the third switch is coupled to the second node; and

the reset control circuit is couple to the third node.

6. The pixel compensation circuit unit according to claim 3 , wherein the first switch is double-gate thin film transistor.

7. The pixel compensation circuit unit according to claim 3 , wherein

the reset control circuit comprises a fourth switch; and

a control electrode of the fourth switch is coupled to the first control power supply line, a first electrode of the fourth switch is coupled to the first node, and a second electrode of the fourth switch is coupled to the reset power supply line.

8. The pixel compensation circuit unit according to claim 4 , wherein

the reset control circuit comprises a fourth switch; and

a control electrode of the fourth switch is coupled to the first control power supply line, a first electrode of the fourth switch is coupled to the second node, and a second electrode of the fourth switch is coupled to the reset power supply line.

9. The pixel compensation circuit unit according to claim 5 , wherein

the reset control circuit comprises a fourth switch; and

a control electrode of the fourth switch is coupled to the first control power supply line, a first electrode of the fourth switch is coupled to the third node, and a second electrode of the fourth switch is coupled to the reset power supply line.

10. A pixel circuit comprising a plurality of pixel compensation circuit units arranged in sequence, wherein

each of the pixel compensation circuit units is the pixel compensation circuit unit of claim 1 .

11. A display device comprising a pixel circuit, wherein the pixel circuit is the pixel circuit of claim 10 .

12. A pixel circuit comprising a plurality of pixel compensation circuit units arranged in sequence, wherein

each of the pixel compensation circuit units is the pixel compensation circuit unit of claim 2 .

13. A pixel circuit comprising a plurality of pixel compensation circuit units arranged in sequence, wherein

each of the pixel compensation circuit units is the pixel compensation circuit unit of claim 3 .

14. A pixel circuit comprising a plurality of pixel compensation circuit units arranged in sequence, wherein

each of the pixel compensation circuit units is the pixel compensation circuit unit of claim 4 .

15. A pixel circuit comprising a plurality of pixel compensation circuit units arranged in sequence, wherein

each of the pixel compensation circuit units is the pixel compensation circuit unit of claim 5 .

16. A display device comprising a pixel circuit, wherein the pixel circuit is the pixel circuit of claim 12 .

17. A display device comprising a pixel circuit, wherein the pixel circuit is the pixel circuit of claim 13 .

18. A display device comprising a pixel circuit, wherein the pixel circuit is the pixel circuit of claim 14 .

19. A display device comprising a pixel circuit, wherein the pixel circuit is the pixel circuit of claim 15 .

20. The pixel compensation circuit unit according to claim 4 , wherein the first switch is double-gate thin film transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2018
From: FENG, YUHSIUNG
To: BOE TECHNOLOGY GROUP CO., LTD.; CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Reel/Frame 047624/0675 →
Priority Claims (1)
CN 201710805843.2 · Sep 8, 2017 · national
Continuity (1)
Related Publication 20210225285A1 · Jul 22, 2021