System and method for transferring data and a data check field

1. A method of operating an integrated circuit, the method comprising:

performing a read operation comprising

receiving a read address on a bus,

decoding the received read address to produce a decoded read address, wherein the decoded read address comprises one or more hardware selection signals;

accessing data from a memory location using the one or more hardware selection signals of the decoded read address,

producing a read data check field based on the accessed data and the one or more hardware selection signals of the decoded read address, and

transmitting the read data check field on the bus.

2. The method of claim 1 , further comprising:

performing a write operation comprising

receiving a write address, write data, and a first write data check field from the bus,

decoding the received write address to produce a decoded write address,

selecting a write location based on the decoded write address,

reading verification data based on the decoded write address before writing the write data,

producing a second write data check field based on the decoded write address and the verification data, and

comparing the first write data check field to the second write data check field, and write the write data to the selected write location when the first write data check field matches the second write data check field based on the comparing.

3. The method of claim 2 , further comprising transmitting an acknowledgement message to the bus when the first write data check field matches the second write data check field based on the comparing.

4. The method of claim 2 , wherein:

writing the write data comprises selecting a first register; and

reading the verification data comprises reading the verification data from the first register.

5. The method of claim 2 , further comprising:

requesting the write operation comprising

determining the first write data check field based on the write address and the write data, and

transmitting the write address, the write data and the first write data check field to the bus.

6. The method of claim 1 , further comprising:

requesting the read operation comprising

transmitting the read address on the bus,

receiving the accessed data and the read data check field from the bus, and

verifying the read data check field from the bus based on received accessed data and the transmitted read address.

7. The method of claim 1 , wherein producing the read data check field comprises:

applying a hash function to the accessed data to produce a first checksum, and

performing a reversible operation with the first checksum and the decoded read address to form the read data check field.

8. The method of claim 7 , wherein the reversible operation comprises an exclusive-OR operation; and

wherein applying the hash function comprises calculating a cyclic redundancy checksum from the accessed data.

9. The method of claim 1 , wherein producing the read data check field comprises mapping the one or more hardware selection signals of the decoded read address to a digital word representative of the one or more hardware selection signals of the decoded read address and producing the read data check field based on the accessed data and the digital word representative of the one or more hardware selection signals of the decoded read address.

10. The method of claim 9 , wherein mapping the one or more hardware selection signals of the decoded read address to the digital word representative of the one or more hardware selection signals of the decoded read address comprises using a multiplexer.

11. The method of claim 1 , wherein the one or more hardware selection signals comprise 1-out-of-N coded individual selection signals.

12. The method of claim 1 , wherein:

the hardware selection signals comprise multiplexer selection signals; and

accessing the data from the memory location using the one or more hardware selection signals of the decoded read address comprises applying the multiplexer selection signals to a multiplexer coupled to the memory location.

13. A battery monitoring system comprising:

a plurality of battery monitoring circuits, each of the plurality of battery monitoring circuits configured to be coupled to a respective battery cell of a battery stack and comprising:

a data circuit configured to calculate a data check field of a data frame from a predetermined identification field and a plurality of data bits, wherein the predetermined identification field represents at least one of a content, source or target of the plurality of data bits; and

a transmitter coupled to the data circuit and configured to transmit the data frame to a host controller via a bus without directly transmitting the predetermined identification field, wherein the data frame comprises the plurality of data bits and the data check field.

14. The battery monitoring system of claim 13 , further comprising the host controller, wherein:

the host controller comprises a receiver configured to receive the plurality of data bits and the data check field from the transmitter via the bus; and

the host controller is configured to determine the predetermined identification field by verifying the data check field based on the received plurality of data bits and a locally stored version of the predetermined identification field.

15. The battery monitoring system of claim 14 , further comprising the battery stack.

16. The battery monitoring system of claim 13 , wherein the plurality of data bits comprises a voltage measurement of the respective battery cell.

17. The battery monitoring system of claim 13 , wherein the data circuit is configured to calculate the data check field by:

performing a reversible operation with the plurality of data bits and the predetermined identification field to produce a first data value; and

applying a hash function to the first data value to produce the data check field.

18. The battery monitoring system of claim 13 , wherein the data circuit is configured to determine the data check field by:

applying a hash function to the plurality of data bits to produce a first checksum; and

performing a reversible operation with the first checksum and the predetermined identification field to produce the data check field.

19. The battery monitoring system of claim 13 , wherein the plurality of battery monitoring circuits are daisy chained together via interconnecting portions of the bus.

20. A method of monitoring a battery, the method comprising:

storing battery sensing data in a register;

receiving a read request from a host controller;

calculating a data check field of a data frame from a predetermined identification field and the stored battery sensing data, wherein the predetermined identification field represents at least one of a content, source or target of the plurality of the battery sensing data; and

in response to the read request, transmitting the data frame to the host controller via a bus without directly transmitting the predetermined identification field, wherein the data frame comprises the battery sensing data and the data check field.

21. The method of claim 20 , wherein the predetermined identification field comprises at least one of a node ID of a battery monitoring circuit or an address of the register.

22. The method of claim 20 , wherein the battery sensing data comprises a measured battery voltage.