IP Library › Granted Patent US 11,114,162

Granted Patent B2

US 11,114,162 · App. 16/810,910 · Granted Sep 7, 2021

Non-volatile semiconductor memory device including a first memory bunch and a second memory bunch

Inventor: Yoshikazu Hosomura (Kamakura, JP)

Assignee: Kioxia Corporation

G11C16/0483 G11C7/18 G11C8/12 G11C8/14 G11C16/08 G11C16/24 H01L27/1157 H01L27/11556 H01L27/11565 H01L27/11582 H01L27/11524

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Quick Facts

Patent No.: US 11,114,162
App. No.: 16/810,910
Granted: Sep 7, 2021
Kind: B2

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Abstract

According to the present embodiment, a semiconductor memory device includes a first memory bunch including a first source line, a first source side selecting gate transistor, a first source side selecting gate line, a plurality of first non-volatile memory cells, a plurality of first word lines, a first drain side selecting gate transistor, a first drain side selecting gate line, and a first bit line; a second memory bunch including, a second source line, a second source side selecting gate transistor, a second source side selecting gate line, a plurality of second non-volatile memory cells, a plurality of second word lines, a second drain side selecting gate transistor, a second drain side selecting gate line, and a second bit line; a common bit line; a first bit line transfer transistor; and a second bit line transfer transistor.

Claims (109)

1. A semiconductor memory device comprising:

a first memory bunch comprising:

a first source line extending in a first direction and a second direction perpendicular to the first direction;

a first source side selecting gate transistor arranged on one side in a third direction intersecting the first direction and the second direction of the first source line;

a first source side selecting gate line connected to a gate of the first source side selecting gate transistor, the first source side selecting gate line extending in the first direction and the second direction;

a plurality of first non-volatile memory cells series connected to the first source side selecting gate transistor, the plurality of first non-volatile memory cells arranged on the one side in the third direction of the first source side selecting gate transistor;

a plurality of first word lines stacked in the third direction and each connected to a gate of a corresponding one of the plurality of first non-volatile memory cells, the plurality of first word lines extending in the first direction and the second direction;

a first drain side selecting gate transistor connected to one of the plurality of first non-volatile memory cells, the first drain side selecting gate transistor arranged on the one side in the third direction of the plurality of first non-volatile memory cells;

a first drain side selecting gate line connected to a gate of the first drain side selecting gate transistor, the first drain side selecting gate line extending in the first direction and the second direction; and

a first bit line connected to the first drain side selecting gate transistor, the first bit line arranged on the one side in the third direction of the first drain side selecting gate line, a longitudinal direction of the first bit line being in the second direction;

a second memory bunch comprising:

a second source line extending in the first direction and the second direction, the second source line arranged on the one side in the third direction of the first bit line;

a second source side selecting gate transistor arranged on the one side in the third direction of the second source line;

a second source side selecting gate line connected to a gate of the second source side selecting gate transistor, the second source side selecting gate line extending in the first direction and the second direction;

a plurality of second non-volatile memory cells series connected to the second source side selecting gate transistor, the plurality of second non-volatile memory cells arranged on the one side in the third direction of the second source side selecting gate transistor;

a plurality of second word lines stacked in the third direction and each connected to a gate of a corresponding one of the plurality of second non-volatile memory cells, the plurality of second word lines extending in the first direction and the second direction and the plurality of second word lines overlapping with the plurality of first word lines in the third direction;

a second drain side selecting gate transistor connected to one of the plurality of second non-volatile memory cells, the second drain side selecting gate transistor arranged on the one side in the third direction of the plurality of second non-volatile memory cells;

a second drain side selecting gate line connected to a gate of the second drain side selecting gate transistor, the second drain side selecting gate line extending in the first direction and the second direction; and

a second bit line connected to the second drain side selecting gate transistor, the second bit line arranged on the one side in the third direction of the second drain side selecting gate line, a longitudinal direction of the second bit line being in the second direction;

a common bit line;

a first bit line transfer transistor connected between the common bit line and the first bit line; and

a second bit line transfer transistor connected between the common bit line and the second bit line.

2. The semiconductor memory device according to claim 1 , further comprising;

a third memory bunch comprising:

a third source line extending in the first direction and the second direction, the third source line arranged on the one side in the third direction of the second bit line;

a third source side selecting gate transistor arranged on the one side in the third direction of the third source line;

a third source side selecting gate line connected to a gate of the third source side selecting gate transistor, the third source side selecting gate line extending in the first direction and the second direction;

a plurality of third non-volatile memory cells series connected to the third source side selecting gate transistor, the plurality of third non-volatile memory cells arranged on the one side in the third direction of the third source side selecting gate transistor;

a plurality of third word lines each connected to a gate of a corresponding one of the plurality of third non-volatile memory cells, the plurality of third word lines extending in the first direction and the second direction;

a third drain side selecting gate transistor connected to one of the plurality of third non-volatile memory cells, the third drain side selecting gate transistor arranged on the one side in the third direction of the plurality of third non-volatile memory cells;

a third drain side selecting gate line connected to a gate of the third drain side selecting gate transistor, the third drain side selecting gate line extending in the first direction and the second direction; and

a third bit line connected to the third drain side selecting gate transistor, the third bit line arranged on the one side in the third direction of the third drain side selecting gate line, a longitudinal direction of the third bit line being in the second direction; and

a third bit line transfer transistor connected between the common bit line and the third bit line,

wherein a longitudinal direction of the common bit line is along the third direction from at least a position corresponding to the third source side selecting gate transistor to a position corresponding to the second drain side selecting gate transistor in the third direction.

3. The semiconductor memory device according claim 2 , further comprising:

a first transfer wiring connecting the common bit line and the first bit line transfer transistor;

a second transfer wiring connecting the common bit line and the second bit line transfer transistor; and

a third transfer wiring connecting the common bit line and the third bit line transfer transistor,

wherein at least a part of a longitudinal direction of each of the first transfer wiring, the second transfer wiring, and the third transfer wiring are arranged in the second direction.

4. The semiconductor memory device according to claim 1 , further comprising:

a first bit line transfer gate line connected to a gate of the first bit line transfer transistor, the first bit line transfer gate line extending in the first direction and the second direction, wherein

the first bit line transfer transistor is arranged on one side in the second direction of the second source side selecting gate transistor, and

a virtual plane extending in the first direction and the second direction passes through the second source side selecting gate line and the first bit line transfer gate line.

5. The semiconductor memory device according to claim 1 , further comprising:

a first bit line transfer gate line connected to a gate of the first bit line transfer transistor, wherein

the first bit line transfer transistor is arranged on one side in the second direction of the first drain side selecting gate transistor, and

a virtual plane extending in the first direction and the second direction passes through the first drain side selecting gate line and the first bit line transfer gate line.

6. The semiconductor memory device according to claim 1 , wherein

the first bit line transfer transistor is arranged between the first bit line and the second source line in the third direction, and

at least a part of the first bit line and at least a part of the first bit line transfer transistor overlap when viewed from the third direction.

7. The semiconductor memory device according to claim 1 , further comprising:

a semiconductor substrate arranged on other side in the third direction of the first source line; and

a CMOS control circuit formed on the semiconductor substrate configured to supply a first control voltage to a gate of the first bit line transfer transistor and supply a second control voltage to a gate of the second bit line transfer transistor.

8. The semiconductor memory device according to claim 1 , further comprising:

a semiconductor substrate arranged on the one side in the third direction of the second bit line; and

9. The semiconductor memory device according to the claim 1 , further comprising:

a first row control circuit arranged between the first bit line and the second source line in the third direction, the first row control circuit configured to supply a voltage to the plurality of first word lines, the first source side selecting gate line, and the first drain side selecting gate line.

10. The semiconductor memory device according to the claim 9 , wherein

the first row control circuit comprises:

a plurality of first word line transfer transistors connected to the plurality of first word lines;

a first source side selecting gate line transfer transistor connected to the first source side selecting gate line; and

a first drain side selecting gate line transfer transistor connected to the first drain side selecting gate line; and

a common selection signal is configured to supply to the gates of the plurality of first word line transfer transistors, the gate of the first source side selection gate line transfer transistor, and the gate of the first drain side selection gate line transfer transistor.

11. The semiconductor memory device according to the claim 10 , wherein the first row control circuit comprises:

a first decode circuit connected to a plurality of bunch selection signal lines, a longitudinal direction of the plurality of the bunch selection signal lines is respectively along the third direction, the first decode circuit configured to output an enable signal; and

a first level shift circuit configured to supply the selection signal based on the enable signal output from the first decode circuit.

12. The semiconductor memory device according to claim 1 , wherein

each of the plurality of first word lines has an substantially plate shape, and

each of the plurality of second word lines has an substantially plate shape.

13. The semiconductor memory device according to claim 12 , wherein

a memory hole penetrates the plurality of first word lines in the third direction, and

in the memory hole, a semiconductor film is formed along the third direction and an insulating film is formed around the semiconductor film.

14. The semiconductor memory device according to claim 13 , wherein the insulating film includes:

a tunnel insulating film formed at an outer periphery of the semiconductor film,

a charge trapping film formed at an outer periphery of the tunnel insulating film, and

a block insulating film formed at an outer periphery of the charge trapping film.

15. A semiconductor memory device comprising:

a first memory bunch comprising:

a first source line extending in a first direction and a second direction perpendicular to the first direction;

a first source side selecting gate transistor arranged on one side in a third direction intersecting the first direction and the second direction of the first source line;

a second memory bunch comprising:

a second source line extending in the first direction and the second direction, the second source line arranged on the one side in the third direction of the first bit line;

a second source side selecting gate transistor arranged on the one side in the third direction of the second source line;

a first vertical bit line connected to the first bit line, a longitudinal direction of the first vertical bit line being in the third direction; and

a second vertical bit line connected to the second bit line, a longitudinal direction of the second vertical bit line being in the third direction,

wherein a longitudinal direction of the first vertical bit line is along the third direction from at least a position corresponding to the second drain side selecting gate transistor to a position corresponding to the second source side selecting gate transistor in the third direction.

16. The semiconductor memory device according to claim 15 , wherein

each of the plurality of first word lines has an substantially plate shape, and

each of the plurality of second word lines has an substantially plate shape.

17. The semiconductor memory device according to claim 16 , wherein

a memory hole penetrates the plurality of first word lines in the third direction, and

in the memory hole, a semiconductor film is formed along the third direction and an insulating film is formed around the semiconductor film.

18. The semiconductor memory device according to claim 17 , wherein the insulating film includes:

a tunnel insulating film formed at an outer periphery of the semiconductor film,

a charge trapping film formed at an outer periphery of the tunnel insulating film, and

a block insulating film formed at an outer periphery of the charge trapping film.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2020

From: HOSOMURA, YOSHIKAZU

To: KIOXIA CORPORATION

Reel/Frame 052034/0425 →

Priority Claims (1)

JP JP2019-152403 · Aug 22, 2019 · national

Continuity (1)

Related Publication 20210057028A1 · Feb 25, 2021

Cited By (1)

US 12,417,962