IP Library › Granted Patent US 11,114,526
Granted Patent B2
US 11,114,526 · App. 16/289,304 · Granted Sep 7, 2021

Semiconductor device

Inventor: Kenichi Matsushita (Nonoichi Ishikawa, JP)
Assignees: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
H01L29/0623H01L29/402H01L29/7304H01L29/7397H01L29/868
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Quick Facts
Patent No.
US 11,114,526
App. No.
16/289,304
Granted
Sep 7, 2021
Kind
B2
Abstract

A semiconductor device includes a semiconductor substrate of a first conductivity type. The semiconductor substrate includes a first semiconductor region of a second conductivity type at a surface thereof, a second semiconductor region of the second conductivity type at the surface and surrounding the first semiconductor region, a third semiconductor region of the second conductivity type provided in the second semiconductor region at the surface and surrounding the first semiconductor region. The third semiconductor region has a concentration of a second conductivity type impurity higher than that of the second semiconductor region. A first insulating film is provided on a part of the first surface at which the second semiconductor region is provided. the first insulating film having an opening that exposes. A first electrode is provided on the first insulating film and electrically connected to the third semiconductor region via the opening.

Claims (27)

1. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type having a first surface and a second surface opposite to the first surface;

an emitter region of the first conductivity type provided in the semiconductor substrate at the first surface;

a base region of a second conductivity type provided in the semiconductor substrate below and adjacent to the emitter region;

a gate electrode provided in the semiconductor substrate at the first surface and surrounding the emitter region and the base region;

a gate insulating film insulating the gate electrode;

a ballast resistance region of the second conductivity type provided in the semiconductor substrate at the first surface and surrounding the gate electrode;

a variation of lateral doping (VLD) region of the second conductivity type provided in the semiconductor substrate at the first surface and surrounding the ballast resistance region;

a semiconductor region of the second conductivity type provided in the ballast resistance region at the first surface, the semiconductor region having a concentration of a second conductivity type impurity higher than that of the ballast resistance region;

a first insulating film provided on a part of the first surface that surrounds the emitter region and corresponds to the ballast resistance region, the first insulating film having a hole at the top of the semiconductor region;

a first-conductivity-type surface semiconductor region provided in the semiconductor substrate at the first surface and surrounding the ballast resistance region, the first-conductivity-type surface semiconductor region having a concentration of a first conductivity type impurity higher than that of the semiconductor substrate; and

a stopper layer of the first conductivity type provided in the semiconductor substrate at the first surface and surrounding the first-conductivity-type surface semiconductor region, a thickness of the stopper layer being greater than a thickness of the first-conductivity-type surface semiconductor region;

a collector region of the first conductivity type provided in the semiconductor substrate at the second surface;

a first electrode provided on the first insulating film and electrically connected to the semiconductor region via the hole;

a second electrode electrically connected to the emitter region, and spaced apart from the first electrode; and

a third electrode electrically connected to the collector region, wherein

the VLD region comprises a plurality of sub-regions, the plurality of sub-regions including a first sub-region surrounding the ballast resistance region, a second sub-region adjacent to and surrounding the first sub-region, and a third sub-region adjacent to and surrounding the second sub-region, the third sub-region positioned at an outer edge of the VLD region, and

a width of the second sub-region in a first direction along the first surface is smaller than a width of the first sub-region in the first direction, and greater than a width of the third sub-region in the first direction.

2. The semiconductor device according to claim 1 , wherein:

the VLD region has a negative concentration gradient of the second conductivity type impurity along the first surface towards a side edge of the semiconductor substrate larger than that of the ballast resistance region.

3. The semiconductor device according to claim 1 , wherein an outer edge of the first electrode includes a wave shape portion.

4. The semiconductor device according to claim 1 , further comprising:

a high-dose semiconductor region of the first conductivity type provided in the semiconductor substrate at a portion of the first surface corresponding to the VLD region, the high-dose semiconductor region having a concentration of a first conductivity type impurity higher than that of the semiconductor substrate.

5. The semiconductor device according to claim 4 , wherein the concentration of the second conductivity type impurity in the ballast resistance region has a maximum value at a first distance in a depth direction from the first surface, the first distance being longer than a thickness of the high-dose semiconductor region.

6. The semiconductor device according to claim 1 , wherein the semiconductor device comprises an insulated gate bipolar transistor (IGBT).

7. The semiconductor device according to claim 1 , wherein a thickness of the fourth semiconductor region above the second sub-region is greater than a thickness of the fourth semiconductor region above the first sub-region and less than a thickness of the fourth semiconductor region above the third sub-region.

8. The semiconductor device according to claim 1 , wherein the VLD region is electrically connected to the base region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2019
From: MATSUSHITA, KENICHI
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 049102/0129 →
Priority Claims (1)
JP JP2018-173140 · Sep 15, 2018 · national
Continuity (1)
Related Publication 20200091283A1 · Mar 19, 2020