Enhancement-mode high electron mobility transistor
Example embodiments relate to enhancement-mode high electron mobility transistors. One embodiment includes a method for manufacturing an enhancement-mode high electron mobility transistor. The method includes providing a stack of layers. The stack of layers includes a substrate, a III-V channel layer over the substrate, a III-V barrier layer on the channel layer, a p-doped III-V layer on the III-V barrier layer, and a Schottky contact interlayer on the p-doped III-V layer. The p-doped III-V layer has a first surface area. The Schottky contact interlayer has a second surface area. The second surface area is less than the first surface area. The second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered. The method also includes depositing a metal gate on the Schottky contact interlayer.
1. A method for manufacturing an enhancement-mode high electron mobility transistor, wherein the method comprises:
providing a stack of layers comprising:
a substrate;
a III-V channel layer over the substrate;
a III-V barrier layer on the III-V channel layer;
a p-doped III-V layer on the III-V barrier layer, wherein the p-doped III-V layer has a first surface area; and
a Schottky contact interlayer on the p-doped III-V layer, wherein the Schottky contact interlayer has a surface that is in contact with the p-doped III-V layer and that has a second surface area, wherein the second surface area is less than the first surface area, and wherein the second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered by the Schottky contact interlayer; and
depositing a metal gate on the Schottky contact interlayer, thereby forming an interface between the metal gate and the Schottky contact interlayer such that entire interface has a third surface area, wherein the third surface area is less than the second surface area.
2. The method of claim 1 , wherein providing the stack of layers comprises:
providing a stack of layers comprising:
the substrate;
the III-V channel layer over the substrate;
the III-V barrier layer on the III-V channel layer;
the p-doped III-V layer on the III-V barrier layer;
the Schottky contact interlayer; and
a hard mask on the Schottky contact interlayer;
laterally wet-etching part of the Schottky contact interlayer to form:
the Schottky contact interlayer having the second surface area; and
a gap between the p-doped III-V layer and the hard mask; and
removing at least part of the hard mask to expose at least part of the Schottky contact interlayer.
3. The method of claim 1 , wherein the III-V channel layer comprises a GaN layer.
4. The method of claim 1 , wherein the III-V barrier layer comprises an AlGaN layer.
5. The method of claim 1 , wherein the Schottky contact interlayer comprises a TiN interlayer.
6. The method of claim 1 , wherein the Schottky contact interlayer has a thickness between 1 nm and 50 nm.
7. The method of claim 1 , wherein the metal gate comprises at least two layers differing in their chemical nature.
8. The method of claim 1 , wherein the metal gate comprises at least one layer comprising Al, Cu, or an alloy of Al and Cu.
9. The method of claim 8 , wherein the metal gate comprises:
a first TiN layer on the Schottky contact interlayer;
a first Ti layer on the first TiN layer;
an alloy of Cu and Al on the first Ti layer;
a second Ti layer on the alloy of Cu and Al; and
a second TiN layer on the second Ti layer.
10. The method of claim 9 , wherein the first TiN layer has a thickness between 10 nm and 80 nm.
11. The method of claim 10 , wherein a combined thickness of the Schottky contact interlayer and the first TiN layer is between from 11 nm to 81 nm.
12. The method of claim 1 , further comprising:
depositing a dielectric layer on the Schottky contact interlayer;
opening part of the dielectric layer to form an opening exposing at least part of the Schottky contact interlayer; and
depositing the metal gate on the Schottky contact interlayer in the opening.
13. The method of claim 12 , wherein depositing the dielectric layer on the Schottky contact interlayer comprises:
depositing an aluminum oxide layer on the Schottky contact interlayer; and
depositing a silicon oxide layer on the aluminum oxide layer.
14. The method of claim 1 , wherein the metal gate comprises a material different from a material forming the Schottky contact interlayer.
15. An enhancement-mode high electron mobility transistor comprising:
a stack of layers comprising:
a substrate:
a III-V channel layer over the substrate;
a III-V barrier layer on the III-V channel layer;
a p-doped III-V layer on the III-V barrier layer, wherein the p-doped III-V layer has a first surface area;
a Schottky contact interlayer on the p-doped III-V layer, wherein the Schottky contact interlayer has a surface that is in contact with the p-doped III-V layer and that has a second surface area, wherein the second surface area is less than the first surface area, and wherein the second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered by the Schottky contact interlayer; and
a metal gate on the Schottky contact interlayer, wherein an interface exists between the metal gate and the Schottky contact interlayer such that the entire interface has a third surface area, wherein the third surface area is less than the second surface area.
16. The enhancement-mode high electron mobility transistor of claim 15 , wherein the III-V channel layer comprises a GaN layer.
17. The enhancement-mode high electron mobility transistor of claim 15 , wherein the III-V barrier layer comprises an AlGaN layer.
18. The enhancement-mode high electron mobility transistor of claim 15 , wherein the Schottky contact interlayer comprises a TiN interlayer.
19. The enhancement-mode high electron mobility transistor of claim 15 , wherein the Schottky contact interlayer has a thickness between 1 nm and 50 nm.
20. The enhancement-mode high electron mobility transistor of claim 15 , wherein the metal gate comprises at least two layers differing in their chemical nature.