IP Library › Granted Patent US 11,119,461
Granted Patent B2
US 11,119,461 · App. 16/423,681 · Granted Sep 14, 2021

Controller

Inventor: Akira Kanemaru (Yamanashi, JP)
Assignee: Fanuc Corporation
G05B19/0405G05B19/19G05B19/4155
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,119,461
App. No.
16/423,681
Granted
Sep 14, 2021
Kind
B2
Abstract

Provided is a controller in which resources can be safely shared by a plurality of processors, such as multi-processors or multi-core processors. The controller is provided with the plurality of processors which each manage the resources or share the resources and include a first processor configured to perform processing with an influence on the integrity of the resources and a second processor. The second processor performs sequence processing for maintaining the integrity of the resources in accordance with the contents of the processing by the first processor, upon receiving a request message requesting the processing to be started.

Claims (10)

1. A controller comprising a plurality of processors which each manage resources or share resources, the controller comprising:

a first processor configured to control a machine; and

a second processor configured to control the machine, wherein the controller is configured to:

control, by the first processor and the second processor, the machine,

transmit, by the second processor, a request message for backup processing to the first processor, the message identifying data sets to be backed up, and enter by the second processor, a second standby state after the transmission of the request message,

when the request message is received, complete processing, by the first processor, the identified data sets for controlling the machine,

when the processing of the identified data sets is complete, transmit, by the first processor, a ready message to the second processor, and enter by the first processor, a first standby state after the transmission of the ready message,

when the ready message is received, perform, by the second processor the backup processing of the identified data sets,

when the backup processing is complete, transmit, by the second processor, an end message to the first processor, and

when the end message is received, resume, by the first processor, controlling the machine.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2019
From: KANEMARU, AKIRA
To: FANUC CORPORATION
Reel/Frame 050179/0435 →
Priority Claims (1)
JP JP2018-106000 · Jun 1, 2018 · national
Continuity (1)
Related Publication 20190369582A1 · Dec 5, 2019