IP Library › Granted Patent US 11,120,188
Granted Patent B2
US 11,120,188 · App. 16/259,490 · Granted Sep 14, 2021

FPGA virtualization

Inventors: Amran A. Al-Aghbari (Dhahran, SA); Muhammad E. S. Elrabaa (Dhahran, SA)
Assignee: King Fahd University of Petroleum and Minerals
G06F30/34G06F9/455H03K19/17728H03K19/17736H03K19/17752H04L67/34
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,120,188
App. No.
16/259,490
Granted
Sep 14, 2021
Kind
B2
Abstract

An FPGA virtualization platform including a network controller configured to provide an interface to an external network; a static logic section coupled to the network controller; and one or more reconfigurable regions each having a virtualized field programmable gate array vFPGA) that includes a wrapper and a user design.

Claims (23)

1. A field programmable gate array virtualization platform comprising:

a network controller configured to provide an interface to an external network;

a plurality of reconfigurable virtualized field programmable gate arrays (vFPGA), wherein each vFPGA is configured to be directly attached to a network via the network controller so as to appear on the network as an independent compute resource to other resources on the network;

a static logic section coupled to the network controller, wherein the static logic section includes a clock management section, a routing arbiter, and a reconfiguration management unit,

wherein the clock management section generates controllable clock domains for each vFPGA,

wherein the routing arbiter routes data from the network controller to a vFPGA through two AXI interconnects, wherein a first AXI interconnect reads from an rx-Async buffer and routes to the vFPGA, wherein a second AXI interconnect reads from the vFPGA and forwards to a tx-Async buffer;

wherein the reconfiguration management unit includes an internal reconfiguration access port (ICAP), has a dedicated MAC/IP address and is configured to download a user design at runtime to one or more vFPGAs, receive partial bitstreams over a network to reconfigure one or more vFPGA, and freeze vFPGA I/O interfaces during configuration or reconfiguration;

each vFPGA including

a wrapper, wherein the wrapper includes a custom interface for the user design that provides data, control, clocking signals and logic for coupling the user design to the static logic section, wherein the custom interface includes a description file, wherein the description file is an extensible mark-up language (XML) file; and

wherein each vFPGA includes a plurality of physical connections which are reconfigured when the user design is received.

2. The field programmable gate array virtualization platform of claim 1 , further comprising:

a wrapper generator, wherein each wrapper is generated by the wrapper generator based on a description file of inputs and outputs of a respective user design.

3. The field programmable gate array virtualization platform of claim 1 , wherein the static logic section presents one or more vFPGAs as a server, each with a separate MAC/IP.

4. The field programmable gate array virtualization platform of claim 1 , wherein the static logic section presents the reconfiguration management unit as a separate server.

5. The field programmable gate array virtualization platform of claim 1 , wherein the network controller includes a transmission control protocol data link, network, and session layers of an OSI network stack.

6. The field programmable gate array virtualization platform of claim 1 , wherein the network controller establishes sessions between vFPGAs and respective clients, and wherein the network controller ensures data ordering and correctness.

7. The field programmable gate array virtualization platform of claim 1 , wherein the network controller is configured to receive user data, deliver the user data to the static logic section, and transmit results back to a user associated with the user data.

8. The field programmable gate array virtualization platform of claim 1 , wherein the network controller is integrated with the static logic section.

9. The field programmable gate array virtualization platform of claim 1 , wherein the network controller is external to the field programmable gate array virtualization platform.

10. The field programmable gate array virtualization platform of claim 1 , wherein a single network controller is shared among a plurality of vFPGAs.

11. The field programmable gate array virtualization platform of claim 1 , wherein a network controller is provided per vFPGA.

12. The field programmable gate array virtualization platform of claim 1 , wherein the static logic section includes data routers configured to route data between the network controller and one or more vFPGA.

13. The field programmable gate array virtualization platform of claim 1 , wherein the reconfiguration management unit includes a wrapper.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2019
From: AL-AGHBARI, AMRAN A.; ELRABAA, MUHAMMAD E. S.
To: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS
Reel/Frame 048157/0870 →
Continuity (1)
Related Publication 20200241899A1 · Jul 30, 2020