Hybrid metallization interconnects for power distribution and signaling
Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a signaling interconnect having a narrow trench disposed within a metallization layer, and a power rail having a wide trench disposed within the metallization layer, wherein the signaling interconnect comprises non-copper material and the power rail comprises copper. The non-copper material may include at least one of ruthenium (Ru), tungsten (W), aluminum (Al), and cobalt (Co). The signaling interconnect and power rail may be processed in a common chemical mechanical polishing step and have approximately the same trench depth. A metal cap may be deposited on top of the power rail.
1. An integrated circuit, comprising:
a signaling interconnect having a narrow trench; and
a power rail having a wide trench;
a first via formed below the narrow trench, and a second via formed below the wide trench,
wherein the signaling interconnect comprises non-copper material and the power rail comprises copper,
wherein the signaling interconnect and the power rail have a common plane processed in a single common chemical mechanical polishing step, and
wherein the first via has a width of approximately 8 to 12 nm, and the second via has a width of approximately 24 to 48 nm.
2. The integrated circuit of claim 1 , wherein the narrow trench has a width of approximately 8 to 12 nm.
3. The integrated circuit of claim 1 , wherein the wide trench has a width of approximately 24 to 48 nm.
4. The integrated circuit of claim 1 , wherein the non-copper material includes at least one of ruthenium (Ru), tungsten (W), aluminum (Al), and cobalt (Co).
5. The integrated circuit of claim 1 , wherein the narrow trench and the wide trench have approximately the same trench depth.
6. The integrated circuit of claim 1 , further comprising a metal cap deposited on top of the power rail.
7. The integrated circuit of claim 6 , wherein the metal cap comprises of cobalt (Co) and has a cap height of approximately 2 to 10 nm.
8. The integrated circuit of claim 1 , further comprising a barrier seed layer formed in the wide trench and the second via.
9. The integrated circuit of claim 8 , wherein the barrier seed layer is approximately 1 nm thick.
10. The integrated circuit of claim 8 , wherein the barrier seed layer comprises titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN).
11. The integrated circuit of claim 1 , further comprising a barrier layer formed in the wide trench, the second via, the narrow trench, and the first via.
12. The integrated circuit of claim 11 , wherein the barrier layer for the narrow trench and the first via is approximately 0.5 nm to 1 nm.
13. The integrated circuit of claim 11 , wherein the barrier layer for the wide trench and the second via is approximately 1 nm.
14. The integrated circuit of claim 1 , wherein the first via is completely filled with a non-copper metallization during deposition.