Device, system and method to determine a power mode of a system-on-chip

1. A system-on-chip (SOC) comprising:

first circuitry to:

receive first signals while the first circuitry is programmed based on multiple criteria which each correspond to a different respective power mode of multiple power modes of the SOC, wherein the first signals indicate a state of the SOC; and

concurrently perform multiple evaluations each based on the state of the SOC and a different respective criteria of the multiple criteria;

second circuitry coupled to receive respective results of the multiple evaluations in parallel from the first circuitry, the second circuitry to select a first power mode based on the results, wherein the second circuitry is to receive the respective results while the second circuitry is programmed with rank information which indicates a relative priorities of the multiple power modes with respect to each other, wherein the second circuitry is to select the first power mode further based on the relative priorities; and

third circuitry, responsive to the second circuitry, to generate second signals to transition the SOC to the first power mode.

2. The SOC of claim 1 , wherein the state comprises multiple conditions, wherein the first signals each correspond to a different respective condition of the multiple conditions, wherein the first circuitry comprises an array of circuit cells, and wherein the first circuitry is to receive first signals while the first circuitry is programmed to correspond circuit cells of the array each to a different respective combination of a test condition and one of the multiple conditions.

3. The SOC of claim 2 , wherein rows of the array each correspond to a different respective criteria of the multiple criteria, and wherein columns of the array each correspond to a different respective condition of the multiple conditions.

4. The SOC of claim 2 , wherein a first cell of the array is to be programmed, comprising the first cell to provide a selection of one of:

a first mode to provide a multi-bit evaluation functionality of the first cell;

a second mode to provide a single-bit evaluation functionality of the first cell; or

a third mode to disable both the multi-bit evaluation functionality and the single-bit evaluation functionality.

5. The SOC of claim 1 , wherein the first circuitry is to be reprogrammed with updated criteria information.

6. The SOC of claim 1 , further comprising fourth circuitry to:

receive sensor signals while the fourth circuitry is programmed with a definition of a format of the first signals; and

generate the first signals based on the sensor signals and the definition of the format.

7. The SOC of claim 1 , wherein the results are to identify a plurality of power modes as candidate power modes, wherein the second circuitry is to select the first power mode based on a determination that, of the candidate power modes, the first power mode is a highest priority power mode.

8. The SOC of claim 1 , wherein the third circuitry is to be programmed with mode transition information which indicates action sequences each to transition to a respective power mode, wherein the second signals are generated based on the mode transition information.

9. The SOC of claim 1 , wherein the first circuitry is coupled to be programmed with a Basic Input/Output System process of the SOC.

10. A system comprising:

an integrated circuit (IC) comprising:

first circuitry to:

receive first signals while the first circuitry is programmed based on multiple criteria which each correspond to a different respective power mode of multiple power modes of the IC, wherein the first signals indicate a state of the IC; and

concurrently perform multiple evaluations each based on the state of the IC and a different respective criteria of the multiple criteria;

second circuitry coupled to receive respective results of the multiple evaluations in parallel from the first circuitry, the second circuitry to select a first power mode based on the results, wherein the second circuitry is to receive the respective results while the second circuitry is programmed with rank information which indicates a relative priorities of the multiple power modes with respect to each other, wherein the second circuitry is to select the first power mode further based on the relative priorities; and

third circuitry, responsive to the second circuitry, to generate second signals to transition the IC to the first power mode; and

a display device coupled to the IC, the display device to display an image based on data communicated with the IC.

11. The system of claim 10 , wherein the state comprises multiple conditions, wherein the first signals each correspond to a different respective condition of the multiple conditions, wherein the first circuitry comprises an array of circuit cells, and wherein the first circuitry is to receive first signals while the first circuitry is programmed to correspond circuit cells of the array each to a different respective combination of a test condition and one of the multiple conditions.

12. The system of claim 11 , wherein rows of the array each correspond to a different respective criteria of the multiple criteria, and wherein columns of the array each correspond to a different respective condition of the multiple conditions.

13. The system of claim 11 , wherein a first cell of the array is to be programmed, comprising the first cell to provide a selection of one of:

a first mode to provide a multi-bit evaluation functionality of the first cell;

a second mode to provide a single-bit evaluation functionality of the first cell; or

a third mode to disable both the multi-bit evaluation functionality and the single-bit evaluation functionality.

14. The system of claim 10 , wherein the IC further comprises fourth circuitry to:

receive sensor signals while the fourth circuitry is programmed with a definition of a format of the first signals; and

generate the first signals based on the sensor signals and the definition of the format.

15. A system-on-chip (SOC) comprising:

an array of circuit cells, the array comprising:

columns which are coupled each to receive a different respective one of first signals which indicate a state of the SOC;

rows to receive a programming which corresponds the rows each to a different respective criterion of multiple criteria which each correspond to a different respective power mode of the SOC, wherein, for each of the rows:

cells of the row are operable each based on a different respective test condition of the corresponding criterion; and

the row is to perform a respective evaluation based on the state of the SOC and the corresponding criterion;

first circuitry coupled to receive evaluation results each from a different respective row of the array, the first circuitry to select a first power mode based on the evaluation results, wherein the first circuitry to select the first power mode based on the evaluation results comprises the first circuitry to identify a plurality of power modes as candidate power modes, and to select the first power mode based on a determination that, of the candidate power modes, the first power mode is a highest priority power mode; and

second circuitry to provide the first power mode responsive to the first circuitry.

16. The SOC of claim 15 , wherein a first cell of the array is operable to select any of:

a first mode wherein a multi-bit evaluation functionality of the first cell is enabled;

a second mode wherein a single-bit evaluation functionality of the first cell is enabled; or

a third mode wherein both the multi-bit evaluation functionality and the single-bit evaluation functionality are disabled.

17. The SOC of claim 15 , further comprising third circuitry which is to:

receive a programming based on a definition of a signal format; and

based on the programming, to generate the first signals according to the signal format.