Method of programming 3D memory device and related 3D memory device

1. A method of programming a channel-stacked memory device which includes a first channel stacked on a second channel, the method comprising:

pre-charging the first channel and the second channel during a first period;

programming a first group of cells in the first channel in a bottom-to-top direction by sequentially programming a 1 st through an m th cells in the first group of cells during a second period subsequent to the first period; and

programming a second group of cells in the second channel in a top-to-bottom direction by sequentially programming a 1 st through an n th cells in the second group of cells during the second period, wherein:

the first channel is controlled by a selected bit line and a top dummy layer formed on a substrate;

the second channel is controlled by the selected bit line and a bottom dummy layer formed on the substrate;

the 1 st cell in the first group of cells is located nearest to the second channel than any other cells in the first group of cells;

the 1 st cell in the second group of cells is located nearest to the first channel than any other cells in the second group of cells; and

m and n are positive integers larger than 1.

2. The method of claim 1 , wherein:

pre-charging the first channel and the second channel comprises:

applying a first voltage to the selected bit line during the first period;

applying a second voltage to a selected top select layer during the first period; and

biasing a selected storage layer in the first group of cells or the second group of cells, a bottom select layer, the top dummy layer and the bottom dummy layer at a ground level;

the top dummy layer and the first group of cells are selectively coupled to the selected bit line via the selected top select layer; and

the bottom dummy layer and the second group of cells are selectively coupled to a source line via the bottom select layer.

3. The method of claim 2 , wherein pre-charging the first channel and the second channel further comprises:

applying a third voltage to a well region of the substrate during the first period.

4. The method of claim 1 , further comprising:

inhibiting an unselected bit line during the first period for allowing channels controlled by the unselected bit line to be floating during the first period.

5. The method of claim 4 , wherein inhibiting the unselected bit line comprises:

applying an inhibit voltage to the unselected bit line during the first period; and

applying a third voltage to an unselected top select layer during the first period.

6. The method of claim 1 , wherein

programming the first channel or the second channel comprises:

ramping a selected storage layer in the first group of cells or the second group of cells to a pass voltage and then to a program voltage during the second period, wherein the program voltage is larger than the pass voltage.

7. The method of claim 6 , wherein programming the first channel or the second channel further comprises:

biasing an unselected cell in the first group of cells or the second group of cells at the pass voltage when programming the selected storage layer in the first group of cells or the second group of cells during the second period.

8. The method of claim 1 , further comprising:

programming the 1 st cell in the first group of cells at a first time point during the second period;

programming the m th cell in the first group of cells at a second time point during the second period;

programming the 1 st cell in the second group of cells at a third time point during the second period; and

programming the n th cell in the second group of cells at a fourth time point during the second period, wherein the first time point is the same as the third time point.

9. The method of claim 1 , further comprising:

programming the 1 st cell in the first group of cells at a first time point during the second period;

programming the m th cell in the first group of cells at a second time point during the second period;

programming the 1 st cell in the second group of cells at a third time point during the second period; and

programming the n th cell in the second group of cells at a fourth time point during the second period, wherein the third time point occurs after the second time point.

10. The method of claim 1 , further comprising:

biasing a middle dummy layer disposed between the first channel and the second channel at a ground level.

11. A memory device, comprising:

a plurality of cells formed on a substrate;

a plurality of bit lines formed on the substrate;

a memory string comprising:

a first channel having a first group of cells and controlled by a selected bit line among the plurality of bit lines and a top dummy layer formed on the substrate;

a second channel having a second group of cells and controlled by the selected bit line and a bottom dummy layer formed in the substrate, wherein the first channel is stacked on the second channel; and

a control unit configured to:

pre-charge the first channel and the second channel during a first period;

program the first group of cells in the first channel in a bottom-to-top direction by sequentially programming a 1 st through an m th cell in the first group of cells during a second period subsequent to the first period; and

program the second group of cells in the second channel in a top-to-bottom direction by sequentially programming a 1 st through an n th cell in the second group of cells during the second period, wherein:

the 1 st cell in the first group of cells is located nearest to the second channel than any other cell in the first group of cells;

the 1 st cell in the second group of cells is located nearest to the first channel than any other cell in the second group of cells; and

m and n are positive integers larger than 1.

12. The memory device of claim 11 , further comprising:

a selected top select layer which selectively couples the top dummy layer and the first group of cells to the selected bit line; and

a bottom select layer which selectively couples the bottom dummy layer and the second group of cells to a source line.

13. The memory device of claim 12 , wherein the control unit is further configured to pre-charge the first channel and the second channel by:

applying a first voltage to the selected bit line during the first period;

applying a second voltage to the selected top select layer during the first period; and

biasing a selected cell in the first group of cells or the second group of cells, the bottom select layer, the top dummy layer and the bottom dummy layer at a ground level.

14. The memory device of claim 11 , wherein the control unit is further configured to inhibit an unselected bit line among the plurality of bit lines during the first period for allowing channels associated with the unselected bit line to be floating during the first period.

15. The memory device of claim 14 , wherein the control unit is further configured to inhibit the unselected bit line during the first period by:

applying a first voltage to the selected bit line during the first period;

applying a second voltage to the selected top select layer during the first period; and

biasing a selected cell in the first group of cells or the second group of cells, the bottom select layer, the top dummy layer and the bottom dummy layer at a ground level.

16. The memory device of claim 11 , wherein the control unit is further configured to program the first channel or the second channel by:

ramping a selected cell in the first group of cells or the second group of cells to a pass voltage and then to a program voltage during the second period, wherein the program voltage is larger than the pass voltage.

17. The memory device of claim 16 , wherein the control unit is further configured to program the first channel or the second channel by:

biasing an unselected cell in the first group of cells or the second group of cells at the pass voltage when programming the selected cell in the first group of cells or the second group of cells during the second period.

18. The memory device of claim 16 , further comprising a middle dummy layer disposed between the first channel and the second channel, wherein the control unit is further configured to bias the middle dummy layer at a ground level.