IP Library Granted Patent US 11,127,694
Granted Patent B2
US 11,127,694 · App. 16/496,767 · Granted Sep 21, 2021

Physical unclonable functions with copper-silicon oxide programmable metallization cells

Inventors: Michael Kozicki (Phoenix, AZ); Wenhao Chen (Folsom, CA)
Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
H01L23/573H01L27/2463H01L45/085H01L45/1233H01L45/1266H01L45/145H01L45/1616H01L45/1625H01L45/1641
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Quick Facts
Patent No.
US 11,127,694
App. No.
16/496,767
Granted
Sep 21, 2021
Kind
B2
Abstract

A physical unclonable functions (PUF) device including a first copper electrode, a second electrode, and a silicon oxide layer positioned directly between the first copper electrode and the second electrode; a method of producing a PUF device; an array comprising a PUF device; and a method of generating a secure key with a plurality of PUF devices.

Claims (26)

1. A physical unclonable functions (PUF) device comprising:

a first copper electrode;

a second electrode;

a layer of silicon oxide positioned directly between and in contact with both the first copper electrode and the second electrode; and

an insulating layer is positioned directly between the second electrode and a circuit.

2. The PUF device of claim 1 , wherein the second electrode comprises W, Ni, Pt, TiN, TaN, TiW, silicon, or polycrystalline silicon.

3. The PUF device of claim 1 , wherein the insulating layer comprises SiO 2 , Si 3 N 4 , or a polymer.

4. The PUF device of claim 1 , wherein a switching operation requires less than or equal to 3 V and less than or equal to 100 μA for less than or equal to 400 μs.

5. An array comprising:

a plurality of copper lines; and

a plurality of lines comprising W, Ni, Pt, TiN, TaN, TiW, or polycrystalline silicon, the plurality of lines positioned perpendicular to the plurality of copper lines;

wherein a PUF device is formed at an intersection of the copper lines and the plurality of lines; and

wherein the intersection comprises a layer of silicon oxide in contact with both the plurality of copper lines and the plurality of lines.

6. The array of claim 5 , wherein the PUF device includes a diode.

7. An integrated circuit comprising the array of claim 5 .

8. A system comprising:

an array of devices, wherein each device comprises

a first copper electrode,

a second electrode,

a layer of silicon oxide positioned directly between and in contact with both the first copper electrode and the second electrode; and

an insulating layer is positioned directly between the second electrode and a circuit,

wherein the array of devices is partitionable such that a portion of the devices generates information and another portion of the array provides memory storage.

9. The system of claim 8 , wherein the devices that generate information are activated to provide a stochastic result.

10. The system of claim 9 , wherein the stochastic result is provided by a change in resistance.

11. The system of claim 8 , wherein the devices that provide memory storage are forced into a deterministic state provided by a stable change in resistance.

12. The system of claim 8 , wherein the array of devices is partitionable based on a change in resistance of the devices.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2019
From: KOZICKI, MICHAEL; CHEN, WENHAO
To: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
Reel/Frame 050463/0414 →
Continuity (2)
Provisional Application 62475725 · Mar 23, 2017
Related Publication 20200381372A1 · Dec 3, 2020
Cited By (3)
US 12,506,624 US 12,527,236 US 12,640,200