IP Library › Granted Patent US 11,127,753
Granted Patent B2
US 11,127,753 · App. 16/816,374 · Granted Sep 21, 2021

Semiconductor storage device and semiconductor storage device manufacturing method

Inventor: Koichi Yamamoto (Yokkaichi, JP)
Assignee: Kioxia Corporation
H01L27/11573H01L21/76802H01L21/76877H01L27/11526H01L27/11582
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Quick Facts
Patent No.
US 11,127,753
App. No.
16/816,374
Granted
Sep 21, 2021
Kind
B2
Abstract

A semiconductor storage device of the embodiment includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked, the stacked body including a stepped portion in which ends of the plurality of conductive layers are stepped, a pillar penetrating the stacked body, the pillar having a memory cell at a height position of each of the plurality of conductive layers, a contact disposed at the stepped portion, the contact being connected to an n-th conductive layer when counted from a lowermost conductive layer of the plurality of conductive layers, and a region in an (n−1)th conductive layer when counted from the lowermost conductive layer of the plurality of conductive layers, the region being disposed at a position below the contact, the region being insulated from the (n−1)th conductive layer surrounding a periphery.

Claims (71)

1. A semiconductor storage device comprising:

a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked, the stacked body including a stepped portion in which ends of the plurality of conductive layers are stepped;

a pillar penetrating the stacked body, the pillar having a memory cell at a height position of each of the plurality of conductive layers;

a contact disposed at the stepped portion, the contact being connected to an n-th conductive layer when counted from a lowermost conductive layer of the plurality of conductive layers where n is an integer of 2 or more; and

a region in an (n−1)th conductive layer when counted from the lowermost conductive layer of the plurality of conductive layers, the region being disposed at a position below the contact, the region being insulated from the (n−1)th conductive layer surrounding a periphery.

2. The semiconductor storage device according to claim 1 , wherein

the region includes

a conductive member embedded in the (n−1)th conductive layer, and

an insulating member surrounding the conductive member.

3. The semiconductor storage device according to claim 1 , wherein

the region

includes an insulating member embedded in the (n−1)th conductive layer.

4. The semiconductor storage device according to claim 1 , wherein

the region

extends to a conductive layer below the (n−1)th conductive layer.

5. The semiconductor storage device according to claim 4 , wherein

the region

extends to the lowermost conductive layer.

6. The semiconductor storage device according to claim 4 , wherein

the region

does not reach the lowermost conductive layer.

7. The semiconductor storage device according to claim 1 , wherein

a contact is connected to each of conductive layers above the n-th conductive layer, and

in each of conductive layers above the (n−1)th conductive layer, the region is disposed at a position below a contact connected to a conductive layer which is one layer above the each conductive layer.

8. The semiconductor storage device according to claim 7 , wherein

a contact is connected to each of conductive layers below the n-th conductive layer, and

the region is not disposed in any of the conductive layers below the (n−1)th conductive layer.

9. The semiconductor storage device according to claim 1 , wherein

the n-th conductive layer

includes, at an end of the stepped portion, a protrusion that protrudes to a step portion of a stage to which the n-th conductive layer belongs.

10. The semiconductor storage device according to claim 1 , wherein

the n-th conductive layer

includes a protrusion surrounding a periphery of the contact.

11. A method of manufacturing a semiconductor storage device, the method comprising:

forming a stacked body in which a plurality of first insulating layers and a plurality of second insulating layers that is later replaced with conductive layers are alternately stacked;

forming a through hole penetrating an (n−1)th second insulating layer when counted from a lowermost second insulating layer of the plurality of second insulating layers where n is an integer of 2 or more;

forming, in the through hole, a region to be insulated from the (n−1)th conductive layer surrounding a periphery when the second insulating layers are replaced with the conductive layers;

forming, in the stacked body, a stepped portion in which ends of the plurality of second insulating layers are stepped; and

forming, above the region in the (n−1)th conductive layer, a contact to be connected to an n-th second insulating layer when counted from a lowermost second insulating layer of the plurality of second insulating layers.

12. The method of manufacturing a semiconductor storage device according to claim 11 , wherein

forming the region includes

forming an insulating member covering an inner wall of the through hole, and

filling a region surrounded by the insulating member with a conductive member.

13. The method of manufacturing a semiconductor storage device according to claim 11 , wherein

forming the region includes

filling the through hole with an insulating member.

14. The method of manufacturing a semiconductor storage device according to claim 11 , wherein

forming the through hole includes

penetrating layers from an uppermost second insulating layer to at least the (n−1)th second insulating layer, and

forming the stepped portion includes

backfilling a portion of the through hole opened in the n-th second insulating layer with an insulating material equivalent to an insulating material of the second insulating layer.

15. The method of manufacturing a semiconductor storage device according to claim 14 , wherein

forming the through hole includes

penetrating a second insulating layer below the (n−1)th second insulating layer.

16. The method of manufacturing a semiconductor storage device according to claim 15 , wherein

forming the through hole includes

penetrating layers up to the lowermost second insulating layer.

17. The method of manufacturing a semiconductor storage device according to claim 15 , wherein

forming the through hole includes

not reaching the lowermost second insulating layer.

18. The method of manufacturing a semiconductor storage device according to claim 11 , wherein

forming the region includes

forming the region in each of second insulating layers above the (n−1)th second insulating layer, and

forming the contact includes

forming the contact above the region in each of conductive layers above the n-th conductive layer.

19. The method of manufacturing a semiconductor storage device according to claim 18 , wherein

forming the contact includes

forming a contact connected to each of conductive layers below the n-th conductive layer.

20. The method of manufacturing a semiconductor storage device according to claim 19 , wherein

forming the region includes

not forming the region in a second insulating layer below the (n−1)th second insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2020
From: YAMAMOTO, KOICHI
To: KIOXIA CORPORATION
Reel/Frame 052475/0110 →
Priority Claims (1)
JP JP2019-151443 · Aug 21, 2019 · national
Continuity (1)
Related Publication 20210057443A1 · Feb 25, 2021