Timer control for peripheral component interconnect express components implemented with thunderbolt controllers
Aspects of the embodiments are directed to systems, methods, and devices for controlling power management entry. A PCIe root port controller can be configured to receive, at a downstream port of the root port controller, from an upstream switch port, a first power management entry request; reject the first power management entry request; transmit a negative acknowledgement message to the upstream switch port; initiate a timer for at least 20 microseconds; during the 20 microseconds, ignore any power management entry requests received from the upstream switch port; receive, after the expiration of the 20 microseconds, a subsequent power management entry request; accept the subsequent power management entry request; and transmit an acknowledgement of the acceptance of the subsequent power management entry request to the upstream switch port.
1. A method for controlling power management request responses, the method comprising:
receiving, at a downstream port of a root port controller compliant with a Peripheral Component Interconnect Express (PCIe) protocol, from an upstream switch port, a first power management entry request;
rejecting the first power management entry request;
transmitting a negative acknowledgement message to the upstream switch port;
initiating a timer for at least 20 microseconds;
during the 20 microseconds, ignoring any power management entry requests received from the upstream switch port;
receiving, after the expiration of the 20 microseconds, a subsequent power management entry request;
accepting the subsequent power management entry request; and
transmitting an acknowledgement of the acceptance of the subsequent power management entry request to the upstream switch port.
2. The method of claim 1 , wherein the first power management request is an active state power management (ASPM) L1 entry request.
3. The method of claim 2 , wherein the upstream port is in an ASPM L0 power management state prior to receiving the ASPM L1 entry request.
4. The method of claim 1 , wherein the power management entry request is received from an upstream switch port of a Thunderbolt device across a converged input/output link.
5. The method of claim 1 , wherein the power management entry request is received from a Thunderbolt device at an integrated Thunderbolt host controller integrated with the downstream port.
6. The method of claim 5 , wherein the power management entry request is received across a Thunderbolt PHY Interface for a PCIe (TBT PIPE) link.
7. The method of claim 1 , wherein the power management entry request comprises a PM_Active_State_Request_L1 data link layer packet (DLLP).
8. The method of claim 1 , wherein the negative acknowledgement message to the upstream switch port comprises a PM_Active_State_Nack transaction layer packet (TLP).
9. The method of claim 1 , wherein the acknowledgement message to the upstream switch port comprises a PM_Enter_Ack packet.
10. The method of claim 1 , wherein ignoring any power management entry requests received from the upstream switch port comprises dropping one or more PM_Active_State_Request_L1 data link layer packets received while the 20 microseconds is counting down to zero.
11. A computing system comprising:
a root port controller compliant with a Peripheral Component Interconnect Express (PCIe) protocol, the root port comprising a downstream port;
a Thunderbolt (TBT) host controller integrated into the computing system and local to the root port controller;
the TBT host controller comprising a PCIe adapter coupled a downstream port of the root port controller by a Thunderbolt PHY Interface for a PCIe (TBT PIPE) link;
the downstream port comprising logic implemented at least partially in hardware, the logic to:
receive, at a downstream port of a root port controller compliant with a Peripheral Component Interconnect Express (PCIe) protocol, from an upstream switch port, a first power management entry request;
reject the first power management entry request;
transmit a negative acknowledgement message to the upstream switch port;
initiate a timer for at least 20 microseconds;
during the 20 microseconds, ignore any power management entry requests received from the upstream switch port;
receive, after the expiration of the 20 microseconds, a subsequent power management entry request;
accept the subsequent power management entry request; and
transmit an acknowledgement of the acceptance of the subsequent power management entry request to the upstream switch port.
12. The computing system of claim 11 , wherein the first power management request is an active state power management (ASPM) L1 entry request.
13. The computing system of claim 12 , wherein the upstream port is in an ASPM L0 power management state prior to receiving the ASPM L1 entry request.
14. The computing system of claim 11 , wherein the power management entry request is received from an upstream switch port of a Thunderbolt device across a converged input/output link.
15. The computing system of claim 11 , wherein the power management entry request is received from a Thunderbolt device at an integrated Thunderbolt host controller integrated with the downstream port.
16. The computing system of claim 15 , wherein the power management entry request is received across a Thunderbolt PHY Interface for a PCIe (TBT PIPE) link.
17. The computing system of claim 11 , wherein the power management entry request comprises a PM_Active_State_Request_L1 data link layer packet (DLLP).
18. The computing system of claim 11 , wherein the negative acknowledgement message to the upstream switch port comprises a PM_Active_State_Nack transaction layer packet (TLP).
19. The computing system of claim 11 , wherein the acknowledgement message to the upstream switch port comprises a PM_Enter_Ack packet.
20. The computing system of claim 11 , wherein ignoring any power management entry requests received from the upstream switch port comprises dropping one or more PM_Active_State_Request_L1 data link layer packets received while the 20 microseconds is counting down to zero.
21. A computer program product tangibly embodied on non-transitory computer-readable media, the computer program product comprising code that when executed cause logic embodied on a root port controller compliant with the Peripheral Component Interconnect Express (PCIe) protocol to:
receive, at a downstream port of a root port controller compliant with a Peripheral Component Interconnect Express (PCIe) protocol, from an upstream switch port, a first power management entry request;
reject the first power management entry request;
transmit a negative acknowledgement message to the upstream switch port;
initiate a timer for at least 20 microseconds;
during the 20 microseconds, ignore any power management entry requests received from the upstream switch port;
receive, after the expiration of the 20 microseconds, a subsequent power management entry request;
accept the subsequent power management entry request; and
transmit an acknowledgement of the acceptance of the subsequent power management entry request to the upstream switch port.
22. The computer program product of claim 21 , wherein the first power management request is an active state power management (ASPM) L1 entry request.
23. The computer program product of claim 22 , wherein the upstream port is in an ASPM L0 power management state prior to receiving the ASPM L1 entry request.
24. The computer program product of claim 21 , wherein the power management entry request is received from an upstream switch port of a Thunderbolt device across a converged input/output link.
25. The computer program product of claim 21 , wherein the power management entry request is received from a Thunderbolt device at an integrated Thunderbolt host controller integrated with the downstream port.