Emission signal driver and display device including the same
An emission signal driver comprises stages connected to emission lines. Each of the stages includes a node controller which supplies a start signal or a carry signal, which is input to a start terminal, to a first node in response to a clock signal input to a clock terminal, a first inverter connected between the first node and a second node, and a second inverter connected between the second node and an output terminal.
1. An emission signal driver comprising stages connected to emission lines,
wherein each of the stages includes:
a node controller which supplies a start signal or a carry signal, which is input to a start terminal, to a first node in response to a clock signal input to a clock terminal;
a first inverter connected between the first node and a second node; and
a second inverter connected between the second node and an output terminal, and
wherein the node controller of a k th stage among the stages includes a first node control transistor which supplies the start signal or the carry signal to the first node in a case in which the clock signal has a gate high voltage, wherein k is a positive integer.
2. The emission signal driver of claim 1 , wherein the first inverter includes:
a first transistor which supplies a gate high voltage to the second node in a case in which the first node has a gate low voltage; and
a second transistor which supplies the gate low voltage to the second node in a case in which the first node has the gate high voltage.
3. The emission signal driver of claim 2 , wherein:
a gate electrode of the first transistor is connected to the first node,
a first electrode of the first transistor is connected to a gate high voltage line through which the gate high voltage is supplied,
a second electrode of the first transistor is connected to the second node; and
a gate electrode of the second transistor is connected to the first node,
a first electrode of the second transistor is connected to a gate low voltage line through which the gate low voltage is supplied, and
a second electrode of the second transistor is connected to the second node.
4. The emission signal driver of claim 1 , wherein the second inverter includes:
a third transistor which supplies a gate high voltage to the output terminal in a case in which the second node has a gate low voltage; and
a fourth transistor which supplies the gate low voltage to the output terminal in a case in which the second node has the gate high voltage.
5. The emission signal driver of claim 4 , wherein:
a gate electrode of the third transistor is connected to the second node,
a first electrode of the third transistor is connected to a gate high voltage line through which the gate high voltage is supplied,
a second electrode of the third transistor is connected to the output terminal; and
a gate electrode of the fourth transistor is connected to the second node,
a first electrode of the fourth transistor is connected to a gate low voltage line through which the gate low voltage is supplied, and
a second electrode of the fourth transistor is connected to the output terminal.
6. The emission signal driver of claim 1 , wherein each of the stages includes a third inverter connected between the second node and a carry signal terminal.
7. The emission signal driver of claim 6 , wherein the third inverter includes:
a fifth transistor which supplies a gate high voltage to the carry signal terminal in a case in which the second node has a gate low voltage; and
a sixth transistor which supplies the gate low voltage to the carry signal terminal in a case in which the second node has the gate high voltage.
8. The emission signal driver of claim 7 , wherein:
a gate electrode of the fifth transistor is connected to the second node,
a first electrode of the fifth transistor is connected to a gate high voltage line through which the gate high voltage is supplied,
a second electrode of the fifth transistor is connected to the carry signal terminal; and
a gate electrode of the sixth transistor is connected to the second node,
a first electrode of the sixth transistor is connected to a gate low voltage line through which the gate low voltage is supplied, and
a second electrode of the sixth transistor is connected to the carry signal terminal.
9. The emission signal driver of claim 2 , wherein each of the stages includes a capacitor connected between the first node and a first driving voltage line.
10. The emission signal driver of claim 1 , wherein
a gate electrode of the first node control transistor is connected to the clock terminal,
a first electrode of the first node control transistor is connected to the first node, and
a second electrode of the first node control transistor is connected to the start terminal.
11. The emission signal driver of claim 1 , wherein the node controller of the (k+1) th stage among the stages includes a second node control transistor which supplies the start signal or the carry signal to the first node in a case in which the clock signal has a gate low voltage.
12. The emission signal driver of claim 11 , wherein
a gate electrode of the second node control transistor is connected to the clock terminal,
a first electrode of the second node control transistor is connected to the start terminal, and
a second electrode of the second node control transistor is connected to the first node.
13. An emission signal driver comprising stages connected to emission lines,
wherein each of the stages includes:
a node controller which supplies a start signal or a carry signal, which is input to a start terminal, to a first node in response to a clock signal input to a clock terminal;
a first inverter connected between the first node and a second node; and
a second inverter connected between the second node and an output terminal, and
wherein the node controller of a k th stage among the stages includes a third node control transistor which supplies the start signal or the carry signal to the first node in a case in which the clock signal has a gate low voltage, wherein k is a positive integer.
14. The emission signal driver of claim 13 , wherein the k th stage further includes a fourth inverter connected between the gate electrode of the third node control transistor and the clock terminal.
15. The emission signal driver of claim 14 , wherein
a gate electrode of the third node control transistor is connected to a fourth inverter,
a first electrode of the third node control transistor is connected to the start terminal, and
a second electrode of the third node control transistor is connected to the first node.
16. The emission signal driver of claim 15 , wherein the fourth inverter includes:
a seventh transistor which supplies a gate high voltage to the gate electrode of the third node control transistor in the case in which the clock signal has the gate low voltage; and
an eighth transistor which supplies the gate low voltage to the gate electrode of the third node control transistor in a case in which the clock signal has the gate high voltage.
17. The emission signal driver of claim 16 , wherein
a gate electrode of the seventh transistor is connected to the clock terminal,
a first electrode of the seventh transistor is connected to a gate high voltage line through which the gate high voltage is supplied,
a second electrode of the seventh transistor is connected to the gate electrode of the first node control transistor,
a gate electrode of the eighth transistor is connected to the clock terminal,
a first electrode of the eighth transistor is connected to a gate low voltage line through which the gate low voltage is supplied, and
a second electrode of the eighth transistor is connected to the gate electrode of the third node control transistor.
18. The emission signal driver of claim 13 , wherein the node controller of the (k+1) th stage among the stages includes a fourth node control transistor which supplies the start signal or the carry signal to the first node in a case in which the clock signal has a gate high voltage.
19. A display device comprising:
pixels connected to emission lines; and
an emission signal driver including stages connected to the emission lines,
wherein each of the stages includes a node controller which supplies a start signal or a carry signal, which is input to a start terminal, to a first node in response to a clock signal input to a clock terminal, a first inverter connected between the first node and a second node, and a second inverter connected between the second node and an output terminal, and
wherein the node controller of a kth stage among the stages includes a node control transistor which supplies the start signal or the carry signal to the first node in a case in which the clock signal has a gate high voltage or a gate low voltage, wherein k is a positive integer.