Method of programming multi-plane memory device for accelerating program speed and reducing program disturbance
A memory device includes a plurality of planes, a row driver and a controller. A method of programming the memory device includes in a program operation, the row driver applying a program pulse to a plurality of memory cells of a first plane of the plurality of planes; after the row driver applies the program pulse to the plurality of memory cells, the controller verifying if the plurality of memory cells have reached a predetermined program state; and if a preset number of the plurality of memory cells have failed to reach the predetermined program state after the plurality of memory cells have been verified for a predetermined number of times, the controller disabling the first plane.
1. A method of programming a memory device, the memory device comprising a plurality of planes, a row driver and a controller, the method comprising:
in a program operation, the row driver applying a program pulse to a plurality of memory cells of a first plane of the plurality of planes;
after the row driver applies the program pulse to the plurality of memory cells, the controller verifying if the plurality of memory cells have reached a predetermined program state; and
if a preset number of the plurality of memory cells have failed to reach the predetermined program state after the plurality of memory cells have been verified for a predetermined number of times, the controller disabling the entire first plane.
2. The method of claim 1 , further comprising:
the controller incrementing a failed verification count when the preset number of the plurality of memory cells have not reached the predetermined program state.
3. The method of claim 1 , wherein predetermined numbers of times associated with failed verifications of the predetermined program state and another program state are identical.
4. The method of claim 1 , wherein predetermined numbers of times associated with failed verifications of the predetermined program state and another program state are different.
5. The method of claim 1 , wherein the controller disabling the first plane comprises:
the controller blocking a plane select signal.
6. The method of claim 1 , wherein the controller disabling the first plane comprises:
the controller blocking a blocks select signal.
7. The method of claim 1 , wherein the controller disabling the first plane comprises:
the controller deselecting all word lines of the first plane.
8. The method of claim 1 , wherein the controller disabling the first plane comprises:
the controller deselecting all bit lines of the first plane.
9. The method of claim 1 , wherein the controller disabling the first plane comprises:
the controller setting a fail bit count pass signal to continue to program the memory device.
10. The method of claim 1 , further comprising:
the controller setting the predetermined program state to a next program state when one of the plurality of planes has passed a verification of the predetermined program state and the predetermined program state is not a highest program state.
11. The method of claim 1 , further comprising:
the controller disabling the plurality of planes when one of the plurality of planes has passed verifications of the predetermined program state and the predetermined program state is a highest program state.