Gate-lifted NMOS ESD protection device
An ESD protection device including a PNP transistor connected to an input pad, a diode connected to the PNP transistor and connected to an output pad, and an NMOS transistor connected to the PNP transistor and the output pad, wherein the diode, PNP transistor, and NMOS transistor are configured to route different levels of an electrostatic discharge (ESD) current pulse from the input pad to the output pad.
1. An electrostatic discharge (ESD) protection device, comprising: a PNP transistor connected to an input pad; a diode having an anode terminal directly connected to a collector of the PNP transistor and a cathode terminal directly connected to an output pad; and an NMOS transistor directly connected to a floating base region of the PNP transistor and the output pad, wherein the diode, the PNP transistor, and the NMOS transistor are configured to route different levels of an electrostatic discharge (ESD) current from the input pad to the output pad, wherein the PNP transistor and the NMOS transistor combine to form a medium current path for the ESD current.
2. The ESD protection device of claim 1 , wherein the ESD protection device is triggered by the PNP transistor in series with the diode.
3. The ESD protection device of claim 2 , wherein a trigger mechanism of the ESD protection device is the floating base region of the PNP transistor in series with the diode.
4. The ESD protection device of claim 3 , wherein the NMOS transistor is in an initial off state because of the floating base region of the PNP transistor.
5. The ESD protection device of claim 1 , wherein the diode and the PNP transistor combine to form a low current path for the ESD current.
6. The ESD protection device of claim 1 , wherein the NMOS transistor and the PNP transistor combine to form an embedded SCR configured to route a high current path for the ESD current.
7. The ESD protection device of claim 1 , wherein a gate of the NMOS transistor is directly connected to the collector of the PNP transistor and to the anode terminal of the diode.
8. The ESD protection device of claim 1 , wherein an emitter of the PNP transistor is connected to the input pad.
9. The ESD protection device of claim 1 , wherein the ESD current is conducted via a channel of the NMOS transistor and a parasitic parallel NPN transistor and boosted at higher current levels via embedded SCR action.
10. The ESD protection device of claim 1 , further comprising:
a first isolation region disposed between the diode and the PNP transistor; and
a second isolation region disposed between the PNP transistor and the NMOS transistor.
11. The ESD protection device of claim 10 , wherein the first isolation region is wider than the second isolation region.
12. The ESD protection device of claim 10 , wherein the PNP transistor has emitter and collector contact regions having a same conductivity type as the first isolation region and the second isolation region.
13. A method of operating an electrostatic discharge (ESD) protection device, comprising:
receiving a low energy current portion of an ESD pulse at an PNP transistor;
conducting the low energy current portion of the ESD pulse to an output pad through a diode having an anode terminal directly connected to a collector of the PNP transistor and a cathode terminal directly connected to the output pad;
receiving a medium energy current portion of the ESD pulse at the PNP transistor;
conducting the medium energy current portion of the ESD pulse to the output pad through an NMOS transistor directly connected to a floating base region of the PNP transistor;
receiving a high energy current portion of the ESD pulse at the PNP transistor and
conducting the high energy current portion of the ESD pulse to the output pad through a silicon controlled rectifier (SCR) formed from the PNP transistor and the NMOS transistor.
14. The method of claim 13 , further comprising:
triggering the ESD protection device using the PNP transistor in series with the diode.
15. The ESD protection device of claim 14 , wherein a trigger mechanism of the ESD protection device is the floating base region of the PNP transistor in series with the diode.
16. The ESD protection device of claim 15 , wherein the NMOS transistor is in an initial off state because of the floating base region of the PNP transistor.
17. The ESD protection device of claim 13 , wherein a gate of the NMOS transistor is directly connected to the collector of the PNP transistor and to the anode terminal of the diode.
18. The ESD protection device of claim 13 , wherein an emitter of the PNP transistor is connected to the input pad.
19. The ESD protection device of claim 13 , wherein the ESD current is conducted via a channel of the NMOS transistor and a parasitic parallel NPN transistor and boosted at higher current levels via embedded SCR action.