Shift register circuit, display panel, and electronic apparatus
Disclosed herein is a shift register circuit that is formed on an insulating substrate with thin film transistors having channels of the same conductivity type and includes shift stages, each of the shift stages including: a first thin film transistor; a second thin film transistor; a 3(1)-th thin film transistor; a 3(2)-th thin film transistor; a 4(1)-th thin film transistor; a 4(2)-th thin film transistor; a fifth thin film transistor; and a sixth thin film transistor.
1. A display device comprising:
a plurality of pixel circuits formed on a substrate; and
a scanning circuit formed on the substrate and configured to selectively output control pulses to the plurality of pixel circuits,
wherein each pixel circuit of the plurality of pixel circuits includes:
a first capacitor;
a sampling transistor configured to write an image signal to the first capacitor in response to a corresponding one of the control pulses;
a drive transistor configured to supply a drive current to a light emitting element in response to the image signal; and
an emission control transistor electrically connected to the drive transistor serially,
wherein the scanning circuit having a plurality of stages, each stage of the plurality of stages including an output node that provides a corresponding one of the control pulses to a corresponding one row of the plurality of pixel circuits, and
the each stage of the plurality of stages includes:
a first transistor having first main electrodes and a first gate electrode, the first main electrodes are electrically connected between a first input node and the output node;
a second transistor having second main electrodes and a second gate electrode, the second main electrodes are electrically connected between a first potential line and the output node;
a third transistor having third main electrodes and a third gate electrode, one of the third main electrodes is electrically connected to the second gate electrode, and the third gate electrode is electrically connected to a third input node;
a fourth transistor having fourth main electrodes and a fourth gate electrode, one of the fourth main electrodes is electrically connected to the first potential line, and the fourth gate electrode is electrically connected to the second gate electrode;
a fifth transistor having fifth main electrodes and a fifth gate electrode, one of the fifth main electrodes is electrically connected to the second gate electrode, and the fifth gate electrode is electrically connected to the first gate electrode; and
a sixth transistor having sixth main electrodes and a sixth gate electrode, one of the sixth main electrodes is electrically connected to the first gate electrode, and the sixth gate electrode is electrically connected to the third input node.
2. The display device according to claim 1 , further comprising a second capacitor electrically connected between the first potential line and the second gate electrode.
3. The display device according to claim 2 , further comprising a third capacitor electrically connected between the first gate electrode and the output node.
4. The display device according to claim 1 , wherein a first ratio of a first channel width to a first channel length of the fifth transistor is equal to or larger than a second ratio of a second channel width to a second channel length of the third transistor.
5. The display device according to claim 4 , wherein the first ratio of the first channel width to the first channel length of the fifth transistor is larger than the ratio of the second channel width to the second channel length of the third transistor.
6. The display device according to claim 1 , wherein the fifth gate electrode is formed on only one side of a channel layer thereof, and the third gate electrode is formed on both sides of the channel layer thereof.
7. The display device according to claim 1 , wherein a first source-shield length of the fifth transistor is smaller than a second source-shield length of the third transistor.
8. The display device according to claim 1 ,
wherein the first input node is configured to receive a first timing signal, and
wherein the third input node is configured to receive a third timing signal.
9. The display device according to claim 1 ,
wherein the first potential line is configured to supply a higher potential than a second potential line.
10. The display device according to claim 1 , wherein the scanning circuit is a same-conductivity-type channel circuit.
11. An electronic apparatus comprising:
a display device including
a plurality of pixel circuits formed on a substrate; and
a scanning circuit formed on the substrate and configured to selectively output control pulses to the plurality of pixel circuits, wherein each pixel circuit of the plurality of pixel circuits includes:
a first capacitor;
a sampling transistor configured to write an image signal to the first capacitor in response to a corresponding one of the control pulses;
a drive transistor configured to supply a drive current to a light emitting element in response to the image signal; and
an emission control transistor electrically connected to the drive transistor serially,
wherein the scanning circuit having a plurality of stages, each stage of the plurality of stages including an output node that provides a corresponding one of the control pulses to a corresponding one row of the plurality of pixel circuits, and
the each stage of the plurality of stages includes:
a first transistor having first main electrodes and a first gate electrode, the first main electrodes are electrically connected between a first input node and the output node;
a second transistor having second main electrodes and a second gate electrode, the second main electrodes are electrically connected between a first potential line and the output node;
a third transistor having third main electrodes and a third gate electrode, one of the third main electrodes is electrically connected to the second gate electrode, and the third gate electrode is electrically connected to a third input node;
a fourth transistor having fourth main electrodes and a fourth gate electrode, one of the fourth main electrodes is electrically connected to the first potential line, and the fourth gate electrode is electrically connected to the second gate electrode;
a fifth transistor having fifth main electrodes and a fifth gate electrode, one of the fifth main electrodes is electrically connected to the second gate electrode, and the fifth gate electrode is electrically connected to the first gate electrode; and
a sixth transistor having sixth main electrodes and a sixth gate electrode, one of the sixth main electrodes is electrically connected to the first gate electrode, and the sixth gate electrode is electrically connected to the third input node.
12. The electronic apparatus according to claim 11 , wherein the display device further includes a second capacitor electrically connected between the first potential line and the second gate electrode.
13. The electronic apparatus according to claim 12 , wherein the display device further includes a third capacitor electrically connected between the first gate electrode and the output node.
14. The electronic apparatus according to claim 11 , wherein a first ratio of a first channel width to a first channel length of the fifth transistor is equal to or larger than a second ratio of a second channel width to a second channel length of the third transistor.
15. The electronic apparatus according to claim 14 , wherein the first ratio of the first channel width to the first channel length of the fifth transistor is larger than the ratio of the second channel width to the second channel length of the third transistor.
16. The electronic apparatus according to claim 11 , wherein the fifth gate electrode is formed on only one side of a channel layer thereof, and the third gate electrode is formed on both sides of the channel layer thereof.
17. The electronic apparatus according to claim 11 , wherein a first source-shield length of the fifth transistor is smaller than a second source-shield length of the third transistor.
18. The electronic apparatus according to claim 11 ,
wherein the first input node is configured to receive a first timing signal, and
wherein the third input node is configured to receive a third timing signal.
19. The electronic apparatus according to claim 11 ,
wherein the first potential line is configured to supply a higher potential than a second potential line.
20. The electronic apparatus according to claim 11 , wherein the scanning circuit is a same- conductivity-type channel circuit.