Semiconductor device and method for fabricating the same
A semiconductor device including a buried insulating layer on a substrate; a lower semiconductor layer on the buried insulating layer, the lower semiconductor layer including a first material; a channel pattern on the lower semiconductor layer, the channel pattern being spaced apart from the lower semiconductor layer and including a second material different from the first material; and a gate electrode surrounding at least a portion of the channel pattern.
1. A semiconductor device, comprising:
a buried insulating layer on a substrate;
a lower semiconductor layer on the buried insulating layer, the lower semiconductor layer including a first material;
a channel pattern on the lower semiconductor layer, the channel pattern being spaced apart from the lower semiconductor layer and including a second material different from the first material;
a gate electrode surrounding at least a portion of the channel pattern; and
a source/drain region on the lower semiconductor layer, the source/drain region being connected to the channel pattern,
wherein the first material includes silicon germanium,
wherein the lower semiconductor layer includes a source/drain recess,
wherein a portion of the source/drain region fills the source/drain recess.
2. The semiconductor device as claimed in claim 1 , wherein:
the first material includes silicon germanium (SiGe), and
a thickness of the lower semiconductor layer is smaller than a thickness of the channel pattern when measured in a same direction.
3. The semiconductor device as claimed in claim 2 , wherein the lower semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer on the first sub-semiconductor layer.
4. The semiconductor device as claimed in claim 3 , wherein:
the first sub-semiconductor layer includes silicon, and
the second sub-semiconductor layer includes silicon germanium.
5. The semiconductor device as claimed in claim 1 , wherein a side surface of the source/drain region has a curved shape.
6. The semiconductor device as claimed in claim 1 , further comprising an inner spacer on a sidewall of the gate electrode.
7. A semiconductor device, comprising:
a lower semiconductor layer on a substrate, the lower semiconductor layer including a first material;
a stacked structure on the lower semiconductor layer, the stacked structure including a conductive pattern and an upper semiconductor layer on the conductive pattern, and the upper semiconductor layer including a second material different from the first material; and
a source/drain region directly contacting the lower semiconductor layer, the source/drain region being connected to the upper semiconductor layer.
8. The semiconductor device as claimed in claim 7 , wherein the conductive pattern includes a gate electrode surrounding at least a portion of the upper semiconductor layer.
9. The semiconductor device as claimed in claim 7 , further comprising a buried insulating layer on the substrate, wherein:
the first material includes silicon germanium, and
the second material includes silicon.
10. The semiconductor device as claimed in claim 7 , wherein the lower semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer on the first sub-semiconductor layer.
11. The semiconductor device as claimed in claim 10 , wherein:
the first sub-semiconductor layer includes silicon, and
the second sub-semiconductor layer includes silicon germanium.
12. The semiconductor device as claimed in claim 11 , wherein a side surface of the source/drain region has a curved shape.
13. The semiconductor device as claimed in claim 7 , further comprising an inner spacer on a sidewall of the stacked structure.
14. A semiconductor device, comprising:
a silicon substrate;
a buried insulating layer on the silicon substrate, the buried insulating layer including an oxide;
a lower semiconductor layer on the buried insulating layer, the lower semiconductor layer including a recess;
a first silicon channel pattern spaced apart from the lower semiconductor layer;
a second silicon channel pattern on the first silicon channel pattern;
a gate electrode on the lower semiconductor layer, the gate electrode surrounding at least a portion of the first silicon channel pattern and the second silicon channel pattern; and
a source/drain region connected to the first silicon channel pattern and the second silicon channel pattern and filling at least a portion of the recess,
wherein:
the lower semiconductor layer includes a material different from materials of the first silicon channel pattern and the second silicon channel pattern,
the lower semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer on the first sub-semiconductor layer,
the first sub-semiconductor layer includes silicon,
the second sub-semiconductor layer includes silicon germanium.
15. The semiconductor device as claimed in claim 14 , wherein:
the lower semiconductor layer includes silicon germanium, and
a thickness of the lower semiconductor layer is smaller than thicknesses of the first silicon channel pattern and the second silicon channel pattern when measured in a same direction.
16. The semiconductor device as claimed in claim 14 , further comprising an inner spacer on the gate electrode.