FinFET device including a stem region of a fin element

1. A device comprising:

a fin disposed on a substrate, wherein the fin includes a passive region, a stem region overlying the passive region, and an active region overlying the stem region, wherein the stem region has a first portion formed of a first semiconductor material and a second portion formed of an oxide material, the second portion being disposed over the first portion, wherein the active region is formed of a second semiconductor material;

a gate structure disposed on the active region, the gate structure including a gate dielectric layer and a gate electrode, wherein the gate dielectric layer physically contacts a sidewall surface of the second portion of the stem region formed of the oxide material at a first interface and the gate electrode physically contacts the sidewall surface of the second portion of the stem region formed of the oxide material at a second interface that is higher above the substrate than the first interface; and

a source/drain feature adjacent the gate structure, wherein the active region, the first portion and the second portion of the stem region extend under a bottommost edge of the source/drain feature.

2. The device of claim 1 , wherein the active region interfaces with the second portion of the stem region.

3. The device of claim 1 , wherein the gate dielectric layer is further disposed on and physically contacting the active region of the stem region.

4. The device of claim 1 , further comprising a shallow trench isolation structure disposed on the substrate, and

wherein the shallow trench isolation structure interfaces with the second portion of the stem region, the first portion of the stem region and the passive region.

5. The device of claim 1 , wherein the active region extends to and physically contacts the bottommost edge of the source/drain feature.

6. The device of claim 1 , wherein the oxide material has a same width from the active region to the first portion of the stem region.

7. The device of claim 1 , wherein the oxide material extends under the bottommost edge of the source/drain feature,

wherein the oxide material disposed under the bottommost edge of the source/drain feature has a top surface facing the bottommost edge of the source/drain feature and an opposing bottom surface facing away from the bottommost edge of the source/drain feature and a sidewall surface connecting the top surface to the bottom surface, and

wherein the first semiconductor material interfaces with the sidewall of the oxide material under the bottommost edge of the source/drain feature.

8. A device comprising:

a fin disposed on a substrate, wherein the fin includes a passive region, a stem region overlying the passive region, and an active region overlying the stem region, wherein the stem region has a first width and the active region has a second width, the first width being different than the second width, and wherein the stem region includes a portion formed of an oxide material having the first width;

a gate structure disposed on the active region, the gate structure including a gate dielectric layer and a gate electrode, wherein the gate dielectric layer physically contacts a sidewall surface of the portion of the stem region formed of the oxide material at a first interface and the gate electrode physically contacts the sidewall surface of the portion of the stem region formed of the oxide material at a second interface that is higher above the substrate than the first interface.

9. The device of claim 8 , further comprising a dielectric isolation structure disposed on the substrate, and

wherein the stem region extends through dielectric isolation structure and the gate electrode to the active region,

wherein the stem region has a third width while extending through the dielectric isolation structure and the first width extending through the gate electrode, the third width being different than the first width.

10. The device of claim 9 , wherein the stem region having the third width is formed of the oxide material.

11. The device of claim 10 , wherein the stem region further includes a first semiconductor material layer extending through the dielectric isolation structure and having the third width, the first semiconductor material layer interfacing with the oxide material having the third width, and

wherein the active region is formed of a second semiconductor material layer having the second width, the second semiconductor material layer interfacing with the oxide material having the first width.

12. The device of claim 11 , wherein the passive region extends from the first semiconductor material layer to under the dielectric isolation structure.

13. The device of claim 8 ,

wherein oxide material having the first width includes a first sidewall and an opposing second sidewall, and

wherein the gate dielectric layer interfaces with the first and second sidewalls of the oxide material having the first width.

14. A device comprising:

a fin disposed on a substrate, wherein the fin includes:

a passive region;

a stem region disposed over the passive region, wherein the stem region includes:

a first semiconductor material layer disposed over and interfacing with the passive region; and

an oxide portion disposed over and interfacing with the first semiconductor material layer; and

an active region disposed over an interfacing with the oxide portion, the active region formed of a second semiconductor material layer;

a gate dielectric layer disposed on the active region and extending to the oxide portion such that the gate dielectric layer physically contacts a sidewall surface of the oxide portion at a first interface; and

a gate electrode layer disposed on the gate dielectric layer and extending to the oxide portion such that the gate electrode layer physically contacts the sidewall surface of the oxide portion at a second interface that is higher above the substrate than the first interface.

15. The device of claim 14 , further comprising a source/drain feature, and

wherein the first semiconductor material layer interfaces with the oxide portion of the stem and the active region directly under the source/drain feature.

16. The device of claim 15 , wherein the source/drain feature interfaces with the active region.

17. The device of claim 14 , wherein the active region has a substantially constant width and the oxide portion has a non-uniform width.

18. The device of claim 14 , further comprising a shallow trench isolation structure disposed on the substrate, and

wherein the shallow trench isolation structure interfaces with the passive region and the stem region of the fin.

19. The device of claim 14 , wherein the second semiconductor material layer includes Si.

20. The device of claim 14 , wherein a portion of the gate electrode layer is disposed directly under the active region of the fin, the portion of the gate electrode layer disposed directly under the active region of the fin is separated from the active region of the fin by a portion of the gate dielectric layer.