Methods for forming three-dimensional phase-change memory devices
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A lower bit line contact and a lower bit line in contact with the lower bit line contact are formed. Lower memory cells are formed above and in contact with the lower bit line. Each lower memory cell includes stacked a phase-change memory (PCM) element, a selector, and electrodes. Parallel word lines in a same plane are formed above and in contact with the lower memory cells. Each word line is perpendicular to the lower bit line. Upper memory cells are formed above and in contact with the word lines. Each upper memory cell includes stacked a PCM element, a selector, and electrodes. An upper bit line is formed above and in contact with the upper memory cells. The upper bit line is perpendicular to each word line. An upper bit line contact is formed above and in contact with the upper bit line. At least one of the lower bit line contact and the upper bit line contact is disposed inclusively between the lower and upper memory cells in a plan view.
1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a lower bit line contact and a lower bit line in contact with the lower bit line contact;
forming a plurality of lower memory cells above and in contact with the lower bit line, each of the lower memory cells comprising stacked a phase-change memory (PCM) element, a selector, and a plurality of electrodes;
forming a plurality of parallel word lines in a same plane above and in contact with the lower memory cells, each of the word lines being perpendicular to the lower bit line;
forming a plurality of upper memory cells above and in contact with the word lines, each of the upper memory cells comprising stacked a PCM element, a selector, and a plurality of electrodes;
forming an upper bit line above and in contact with the upper memory cells, the upper bit line being perpendicular to each of the word lines; and
forming an upper bit line contact above and in contact with the upper bit line,
wherein at least one of the lower bit line contact and the upper bit line contact is disposed inclusively between the lower and upper memory cells in a plan view.
2. The method of claim 1 , wherein
the lower bit line contact is disposed inclusively between the lower memory cells in the plan view; and
forming the lower bit line contact comprises in-situ polymer deposition and etching, such that a critical dimension of the lower bit line contact is not greater than a critical dimension of the lower bit line.
3. The method of claim 1 , wherein
the upper bit line contact is disposed inclusively between the upper memory cells in the plan view; and
forming the upper bit line contact comprises in-situ polymer deposition and etching, such that a critical dimension of the upper bit line contact is not greater than a critical dimension of the upper bit line.
4. The method of claim 1 , wherein forming the plurality of lower memory cells or the upper memory cells comprises:
subsequently depositing layers of a first conductor, an ovonic threshold switch (OTS) material, a second conductor, a chalcogenide-based alloy, and a third conductor to form a memory stack; and
subsequently etching the memory stack in two perpendicular directions.
5. The method of claim 4 , wherein subsequently etching the memory stack comprises:
double patterning the memory stack in a first direction of the two perpendicular directions;
etching the double-patterned memory stack in the first direction to form a first gap;
filling the first gap with a dielectric material;
double patterning the etched memory stack in a second direction of the two perpendicular directions;
etching the double-patterned, etched memory stack in the second direction to form a second gap; and
filling the second gap with the dielectric material.
6. The method of claim 1 , wherein forming the lower bit line, the word lines, or the upper bit line comprises:
depositing a layer of conductor;
double patterning the layer of conductor; and
etching the double-patterned layer of conductor.
7. A method for forming a three-dimensional (3D) memory device, comprising:
forming a lower bit line contact and a lower bit line in contact with the lower bit line contact;
forming a plurality of lower memory cells above and in contact with the lower bit line, each of the lower memory cells comprising stacked a phase-change memory (PCM) element, a selector, and a plurality of electrodes, wherein the lower bit line contact is disposed inclusively between the lower memory cells in a plan view;
forming a plurality of parallel word lines in a same plane above and in contact with the lower memory cells, each of the word lines being perpendicular to the lower bit line;
forming an upper bit line contact and a plurality of upper memory cells above the word lines, each of the upper memory cells being in contact with a respective one of the word lines and comprising stacked a PCM element, a selector, and a plurality of electrodes, wherein a top surface of each of the upper memory cells is flush with a top surface of the upper bit line contact; and
forming an upper bit line above and in contact with the upper memory cells and the upper bit line contact.
8. The method of claim 7 , wherein
forming the lower bit line contact comprises in-situ polymer deposition and etching, such that a critical dimension of the lower bit line contact is not greater than a critical dimension of the lower bit line; and
forming the upper bit line contact comprises in-situ polymer deposition and etching, such that a critical dimension of the upper bit line contact is not greater than a critical dimension of the upper bit line.
9. The method of claim 7 , wherein forming the plurality of lower memory cells or the upper memory cells comprises:
subsequently depositing layers of a first conductor, an ovonic threshold switch (OTS) material, a second conductor, a chalcogenide-based alloy, and a third conductor to form a memory stack; and
subsequently etching the memory stack in two perpendicular directions.
10. The method of claim 9 , wherein subsequently etching the memory stack comprises:
double patterning the memory stack in a first direction of the two perpendicular directions;
etching the double-patterned memory stack in the first direction to form a first gap;
filling the first gap with a dielectric material;
double patterning the etched memory stack in a second direction of the two perpendicular directions;
etching the double-patterned, etched memory stack in the second direction to form a second gap; and
filling the second gap with the dielectric material.
11. The method of claim 7 , wherein forming the lower bit line, the word lines, or the upper bit line comprises:
depositing a layer of conductor;
double patterning the layer of conductor; and
etching the double-patterned layer of conductor.
12. A method for forming a three-dimensional (3D) memory device, comprising:
forming a lower bit line contact and a lower bit line in contact with the lower bit line contact,
forming a plurality of lower memory cells above and in contact with the lower bit line, each of the lower memory cells comprising stacked a phase-change memory (PCM) element, a selector, and a plurality of electrodes;
forming a plurality of parallel word lines in a same plane above and in contact with the lower memory cells, each of the word lines being perpendicular to the lower bit line;
forming a plurality of upper memory cells above and in contact with the word lines, each of the upper memory cells comprising stacked a PCM element, a selector, and a plurality of electrodes;
forming an upper bit line above and in contact with the upper memory cells, the upper bit line being perpendicular to each of the word lines; and
forming an upper bit line contact in contact with the upper bit line,
wherein a critical dimension of at least one of the lower bit line contact and the upper bit line contact is not greater than a critical dimension of the corresponding lower bit line or upper bit line.
13. The method of claim 12 , wherein forming the lower bit line contact or the upper bit line contact comprises in-situ polymer deposition and etching.
14. The method of claim 12 , wherein the critical dimension of the at least one of the lower and upper bit line contacts is not greater than about 60 nm.
15. The method of claim 14 , wherein the critical dimension of the at least one of the lower and upper bit line contacts is between about 10 nm and about 30 nm.
16. The method of claim 12 , wherein the at least one of the lower and upper bit line contacts has a same pitch as the corresponding lower bit line or upper bit line.
17. The method of claim 12 , wherein the critical dimension of each of the lower and upper bit line contacts is not greater than the critical dimension of each of the lower and upper bit lines.
18. The method of claim 12 , wherein forming the plurality of lower memory cells or the upper memory cells comprises:
subsequently depositing layers of a first conductor, an ovonic threshold switch (OTS) material, a second conductor, a chalcogenide-based alloy, and a third conductor to form a memory stack; and
subsequently etching the memory stack in two perpendicular directions.
19. The method of claim 18 , wherein subsequently etching the memory stack comprises:
double patterning the memory stack in a first direction of the two perpendicular directions;
etching the double-patterned memory stack in the first direction to form a first gap;
filling the first gap with a dielectric material;
double patterning the etched memory stack in a second direction of the two perpendicular directions;
etching the double-patterned, etched memory stack in the second direction to form a second gap; and
filling the second gap with the dielectric material.
20. The method of claim 12 , wherein forming the lower bit line, the word lines, or the upper bit line comprises:
depositing a layer of conductor;
double patterning the layer of conductor; and
etching the double-patterned layer of conductor.