IP Library › Granted Patent US 11,133,568
Granted Patent B2
US 11,133,568 · App. 16/233,040 · Granted Sep 28, 2021

Semiconductor package structure having antenna module

Inventors: Yenheng Chen (Jiangyin, CN); Chengtar Wu (Jiangyin, CN); Chengchung Lin (Jiangyin, CN)
Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
H01Q1/2283H01L23/49811H01L23/49822H01L23/5226H01L23/5386H01L23/53228H01L23/53257H01L23/66H01L24/14H01L24/95H01Q1/36H01Q1/364H01Q21/08H01L23/15H01L23/49816H01L2223/6677H01L2224/16227H01L2224/32225H01L2224/73204H01L2224/92125H01L2924/15321
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,133,568
App. No.
16/233,040
Granted
Sep 28, 2021
Kind
B2
Abstract

A semiconductor package structure having an antenna module includes: a substrate, having a first surface, a second surface, and at least one via hole made by a laser running through the substrate; a rewiring layer, disposed on the first surface of the substrate; metal bumps, disposed on the rewiring layer and electrically connected to the rewiring layer; a semiconductor chip, disposed on and electrically connected to the rewiring layer; a conductive column, filling the via hole, and an antenna module, disposed on the second surface of the substrate and electrically connected to the metal bumps through the conductive column and the rewiring layer.

Claims (24)

1. A semiconductor package structure having an antenna module, comprising:

a substrate, having a first surface and a second surface opposite to the first surface, wherein at least one via hole running through the first surface and the second surface is formed in the substrate;

a rewiring layer, disposed on the first surface of the substrate;

a plurality of metal bumps, disposed on and electrically connected to the rewiring layer;

a semiconductor chip, disposed on and electrically connected to the rewiring layer, wherein a lateral space is configured between the semiconductor chip and each of the plurality of metal bumps;

a conductive column, filling the via hole; and

an antenna module, disposed on the second surface of the substrate, wherein the antenna module is electrically connected to the plurality of metal bumps through the conductive columns and the rewiring layer;

wherein the antenna module comprises a plurality of antenna units having a same contour, and arranged with a space from each other;

wherein the plurality of antenna units each comprises a central portion and a peripheral portion surrounding the central portion, wherein a space is set between the peripheral portion and the central portion; and

wherein the central portion is electrically connected to one of the plurality of metal bumps through the conductive column and the rewiring layer.

2. The semiconductor package structure having the antenna module according to claim 1 , wherein the semiconductor package structure further comprises an underfill layer, wherein the underfill layer fills a gap between the semiconductor chip and the rewiring layer.

3. The semiconductor package structure having the antenna module according to claim 1 , wherein the substrate is a quartz glass substrate or a sapphire substrate.

4. The semiconductor package structure having the antenna module according to claim 1 , wherein the rewiring layer comprises:

a dielectric layer, bonded onto the first surface of the substrate;

at least one metal wire layer, wherein the metal wire layer is patterned into the dielectric layer; and

an under-bump metal layer, patterned into the dielectric layer, wherein the under-bump metal layer is electrically connected to the at least one metal wire layer; and

wherein the plurality of metal bumps is disposed directly on the under-bump metal layer.

5. The semiconductor package structure having the antenna module according to claim 1 , wherein the plurality of metal bumps each comprises: a copper column, a nickel layer disposed on a top surface of the copper column, and a solder bump disposed under the nickel layer.

6. The semiconductor package structure having the antenna module according to claim 1 , wherein a shape of the central portion is a circle, an outer circumvent of the peripheral portion is a square, and an inner circumvent of the peripheral portion is a circle.

7. The semiconductor package structure having the antenna module according to claim 1 , wherein the plurality of antenna units is arranged in an array.

8. The semiconductor package structure having the antenna module according to claim 7 , wherein the array is has a ring shape.

9. The semiconductor package structure having the antenna module according to claim 1 , wherein the antenna units are arranged irregularly spaced on the second surface of the substrate.

10. The semiconductor package structure having the antenna module according to claim 1 , wherein the antenna module comprises at least two layers of antenna module unit, and each layer of the antenna module unit comprises at least one antenna unit.

11. The semiconductor package structure having the antenna module according to claim 1 , wherein the via hole is made by laser drilling.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2021
From: CHEN, YENHENG; WU, CHENGTAR; LIN, CHENGCHUNG
To: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
Reel/Frame 055193/0463 →
Priority Claims (1)
CN 201721855634.0 · Dec 27, 2017 · national
Continuity (1)
Related Publication 20190198973A1 · Jun 27, 2019