Video input port
In the described examples, a video integrated circuit (IC) chip includes a video input port (VIP) that receives a video stream. The video IC chip also includes a processing unit coupled to a non-transitory memory and is configured to detect the presence of a data stream provided to the VIP, cause the VIP to switch a target partition for the data stream from a given partition in the memory to another partition in the memory and to write the data stream to the other partition in the memory.
1. An integrated circuit (IC) chip, comprising:
a memory comprising a first partition and a second partition;
a general purpose input/output (GPIO) pin configured to receive a control signal the control signal indicating a data stream;
a video input port (VIP) coupled to the memory, comprising a video port direct memory access, and configured to receive a video stream and a data stream; and
a processing unit coupled to the GPIO pin and the VIP, the processing unit configured to:
determine whether an operation mode is a first operation mode corresponding to a video stream mode or a second operation mode corresponding to a data stream mode based on the received control signal;
in response to determining the operation mode is the first operation mode, cause the VIP to transfer the received video stream to the first partition of the memory in a direct memory access write using the video port direct memory access; and
in response to determining the operation mode is the second operation mode, cause the VIP to transfer the received data stream to the second partition of the memory in the direct memory access write using the video port direct memory access.
2. The IC chip of claim 1 , wherein the video stream is received from a remote IC chip via a video medium over a cable.
3. The IC chip of claim 2 , wherein the video medium comprises:
a first transmit and receive module configured to communicate with the remote IC chip; and
a second transmit and receive module configured to communicate with the video IC chip.
4. The IC chip of claim 3 , wherein the first transmit and receive module and the second transmit and receive module communicate via a serial communication channel.
5. The IC chip of claim 4 , wherein the serial communication channel is a low voltage differential signaling (LVDS) channel.
6. The IC chip of claim 4 , wherein the serial communication channel comprises a one-way data link and a bi-directional control channel.
7. The IC chip of claim 1 , wherein the VIP is configured to receive the video stream and the data stream concurrently.
8. The IC chip of claim 1 , wherein the IC chip is configured to drive a display with the video stream.
9. A system, comprising:
a video medium circuit adapted to be coupled to a remote integrated circuit (IC) chip and configured to receive a video stream, data stream, and a control signal;
a video IC chip, comprising: a memory comprising a first partition and a second partition;
a general purpose input/output (GPIO) pin configured to receive the control signal from the video medium circuit, the control signal indicating a data stream;
a video input port (VIP) coupled to the memory, comprising a video port direct memory access, and configured to receive the video stream and the data stream from the video medium circuit; and
a processing unit coupled to the GPIO pin and the VIP, the processing unit configured to:
determine whether an operation mode is a first operation mode corresponding to a video stream mode or a second operation mode corresponding to a data stream mode based on the received control signal;
in response to determining the operation mode is the first operation mode, cause the VIP to transfer the received video stream to the first partition of the memory in a direct memory access write using the video port direct memory access; and
in response to determining the operation mode is the second operation mode, cause the VIP to transfer the received data stream to the second partition of the memory in the direct memory access write using the video port direct memory access.
10. The system of claim 9 , wherein the video medium circuit comprises:
a deserializer; and
a serializer configured to:
receive the video stream and the control signal from the remote IC chip: and
serialize the videos stream and the control signal for communication on a communication channel between the serializer and the deserializer;
wherein the deserializer is configured to:
de-serialize the video stream and the control signal; and
provide the video stream to the VIP of the video IC chip.
11. The system of claim 10 , wherein the serializer is configured to receive the control signal from a GPIO pin of the remote IC chip, and the deserializer is configured to provide the control signal to the GPIO pin of the video IC chip.
12. The system of claim 10 , wherein the control signal identifies a time that the data stream is provided to the VIP of the video IC chip.
13. The system of claim 9 , wherein the video medium circuit provides the only communication path between the video IC chip and the remote IC chip.
14. The IC chip of claim 1 , wherein the data stream comprises a firmware or a software update for the IC chip.