IP Library › Granted Patent US 11,137,921
Granted Patent B2
US 11,137,921 · App. 16/560,417 · Granted Oct 5, 2021

Data storage device and system

Inventors: Young Jin Cho (Seoul, KR); Hyo Deok Shin (Seoul, KR); Kyung Bo Yang (Hwaseong-si, KR); Youn Ho Jeon (Gimhae-si, KR); Hyeok Jun Choe (Hwaseong-si, KR); Jung Hyun Hong (Hwaseong-si, KR); Soon Suk Hwang (Ansan-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
G06F3/064G06F3/061G06F3/0608G06F3/0616G06F3/0644G06F3/0656G06F3/0679
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Quick Facts
Patent No.
US 11,137,921
App. No.
16/560,417
Granted
Oct 5, 2021
Kind
B2
Abstract

A data storage device is provided. The data storage device includes: a first function block of a device controller configured to receive user data and perform a first data processing; a first buffer memory connected to the first function block and configured to store user data subjected to the first data processing as first process data; a second function block of the device controller configured to receive a data write command determined based on the first process data; and a non-volatile memory connected to the second function block, and configured to receive and store data stored in the first buffer memory. The user data is provided to the first function block before the data write command is provided to the second function block.

Claims (43)

1. A data storage device comprising:

a device controller configured to implement a first hardware function block and a second hardware function block configured to perform functions independent of the first hardware function block;

a first buffer memory connected to the first hardware function block;

a second buffer memory connected to the second hardware function block and configured to interface with another device that is external to the data storage device; and

a non-volatile memory connected to the first hardware function block,

wherein the first hardware function block and the second hardware function block are connected to each other and configured to directly exchange data,

wherein the first hardware function block is configured to receive first process data from the second hardware function block in accordance with a data write command and write the first process data to the non-volatile memory,

wherein the second hardware function block is configured to receive user data and generate second process data by performing first data processing based on the user data,

wherein the second hardware function block is configured to store the second process data in the second buffer memory,

wherein the first process data is generated based on the second process data, and

wherein the data write command is generated based on the first process data.

2. The data storage device of claim 1 , wherein the first buffer memory is not configured to interface with the another device that is external to the data storage device.

3. The data storage device of claim 1 , wherein the second buffer memory is configured to store the first process data, and

wherein the second hardware function block is configured to read the first process data from the second buffer memory, and directly provide the first process data to the first hardware function block.

4. The data storage device of claim 1 , wherein the first hardware function block is configured to read the first process data from the non-volatile memory in accordance with a data read command and provide the first process data to the second hardware function block.

5. The data storage device of claim 4 , wherein the second hardware function block is configured to execute third data processing based on the first process data to generate third process data.

6. The data storage device of claim 1 , wherein the first hardware function block is configured to read the first process data from the non-volatile memory in accordance with a data read command and provide the first process data to the external of the data storage device.

7. The data storage device of claim 1 , wherein the first hardware function block, the first buffer memory, and the non-volatile memory are connected by a non-volatile memory express (NVMe) interface.

8. The data storage device of claim 1 , wherein the first hardware function block and the second hardware function block are connected via a bridge in an end point of a Peripheral Component Interconnect Express (PCIe).

9. The data storage device of claim 1 , wherein the second hardware function block comprises at least one from among a data compression engine, a data encryption engine, a data scanning engine, a data filtering engine, a data hashing engine and a neural network engine.

10. A data storage device comprising:

a first hardware function block of a device controller configured to receive user data and perform a first data processing to generate first process data;

a first buffer memory connected to the first hardware function block and configured to store user data subjected to the first data processing as the first process data;

a second hardware function block of the device controller configured to receive a data write command determined based on the first process data; and

a non-volatile memory connected to the second hardware function block and configured to receive and store data stored in the first buffer memory,

wherein the user data corresponding to the first process data is provided to the first hardware function block before the data write command corresponding to the first process data is provided to the second hardware function block,

wherein the first buffer memory is configured to store second process data, and

wherein the second process data is generated based on the first process data.

11. The data storage device of claim 10 , wherein the first hardware function block and the second hardware function block are connected to each other and configured to directly exchange data.

12. The data storage device of claim 10 , wherein the first buffer memory is configured to interface with another device that is external to the data storage device.

13. A data storage system comprising:

a host processor configured to generate a data write command and a data read command; and

a data storage device comprising a device controller configured to communicate with the host processor,

wherein the device controller is configured to receive user data before receiving the data write command from the host processor,

wherein the device controller is configured to provide first process data to the host processor based on the data read command, and

wherein the first process data is data generated by the device controller and the host processor based on the user data.

14. The data storage system of claim 13 , wherein the device controller is configured to generate second process data based on the user data received from the host processor, and

wherein the host processor is configured to generate the first process data based on the second process data and generate the data write command based on the first process data.

15. The data storage system of claim 14 , wherein the device controller is configured to store the first process data in the data storage device based on the device controller receiving the data write command, and

wherein the device controller is configured to provide the first process data to the host processor based on the device controller receiving the data read command.

16. The data storage system of claim 13 , further comprising a host memory connected to the host processor,

wherein the host memory is configured to store metadata of the first process data.

17. The data storage system of claim 13 , wherein the host processor and the data storage device are connected by a Peripheral Component Interconnect Express (PCIe) bus.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2019
From: CHO, YOUNG JIN; SHIN, HYO DEOK; YANG, KYUNG BO; JEON, YOUN HO; CHOE, HYEOK JUN; HONG, JUNG HYUN; HWANG, SOON SUK
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 050266/0783 →
Priority Claims (1)
KR 10-2019-0025059 · Mar 5, 2019 · national
Continuity (1)
Related Publication 20200285392A1 · Sep 10, 2020