Multi-tenant encryption for storage class memory
Various embodiments are generally directed to the providing for mutual authentication and secure distributed processing of multi-party data. In particular, an experiment may be submitted to include the distributed processing of private data owned by multiple distrustful entities. Private data providers may authorize the experiment and securely transfer the private data for processing by trusted computing nodes in a pool of trusted computing nodes.
1. An apparatus, comprising:
a processor; and
memory comprising instructions that when executed by the processor cause the processor to:
receive a memory access request including an indication of a first physical address, the first physical address including an indication of a unique tenant identification and a second physical address; and
access a storage class memory (SCM) based on the second physical address and a tenant key corresponding to the unique tenant identification.
2. The apparatus of claim 1 , the memory comprising instructions that when executed by the processor cause the processor to translate the second physical address from a first domain to a second domain.
3. The apparatus of claim 2 , the first domain comprising a virtual domain and the second domain comprising a host domain.
4. The apparatus of claim 2 , the memory comprising instructions that when executed by the processor cause the processor to add the translated second physical address to a context table.
5. The apparatus of claim 4 , the context table for an input/output (I/O) memory access.
6. The apparatus of claim 4 , the memory comprising instructions that when executed by the processor cause the processor to add an indication of a second unique tenant identification to the context table.
7. The apparatus of claim 6 , the second unique tenant identification corresponding to an input/output (I/O) device.
8. The apparatus of claim 1 , the second physical address comprising a physical address of the SCM.
9. The apparatus of claim 1 , the memory comprising instructions that when executed by the processor cause the processor to retrieve an information element from the SCM based on a memory access to the second physical address and the tenant key corresponding to the unique tenant identification.
10. At least one non-transitory computer-readable medium comprising a set of instructions that, in response to being executed by a processor circuit, cause the processor circuit to:
receive a memory access request including an indication of a first physical address, the first physical address including an indication of a unique tenant identification and a second physical address; and
access a storage class memory (SCM) based on the second physical address and a tenant key corresponding to the unique tenant identification.
11. The at least one non-transitory computer-readable medium of claim 10 , comprising instructions that, in response to being executed by the processor circuit, cause the processor circuit to translate the second physical address from a first domain to a second domain.
12. The at least one non-transitory computer-readable medium of claim 11 , the first domain comprising a virtual domain and the second domain comprising a host domain.
13. The at least one non-transitory computer-readable medium of claim 11 , comprising instructions that, in response to being executed by the processor circuit, cause the processor circuit to add the translated second physical address to a context table.
14. The at least one non-transitory computer-readable medium of claim 13 , the context table for an input/output (I/O) memory access.
15. The at least one non-transitory computer-readable medium of claim 13 , comprising instructions that, in response to being executed by the processor circuit, cause the processor circuit to add an indication of a second unique tenant identification to the context table.
16. The at least one non-transitory computer-readable medium of claim 15 , the second unique tenant identification corresponding to an input/output (I/O) device.
17. The at least one non-transitory computer-readable medium of claim 10 , the second physical address comprising a physical address of the SCM.
18. The at least one non-transitory computer-readable medium of claim 10 , comprising instructions that, in response to being executed by the processor circuit, cause the processor circuit to retrieve an information element from the SCM based on a memory access to the second physical address and the tenant key corresponding to the unique tenant identification.
19. A computer-implemented method, comprising:
receiving a memory access request including an indication of a first physical address, the first physical address including an indication of a unique tenant identification and a second physical address; and
accessing a storage class memory (SCM) based on the second physical address and a tenant key corresponding to the unique tenant identification.
20. The computer-implemented method of claim 19 , comprising translating the second physical address from a first domain to a second domain.
21. The computer-implemented method of claim 20 , the first domain comprising a virtual domain and the second domain comprising a host domain.
22. The computer-implemented method of claim 20 , comprising adding the translated second physical address to a context table.
23. The computer-implemented method of claim 22 , the context table for an input/output (I/O) memory access.
24. The computer-implemented method of claim 22 , comprising adding an indication of a second unique tenant identification to the context table.
25. The computer-implemented method of claim 19 , comprising retrieving an information element from the SCM based on a memory access to the second physical address and the tenant key corresponding to the unique tenant identification.