Hybrid gate stack integration for stacked vertical transport field-effect transistors
A method of forming a semiconductor structure includes forming one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor (VTFET) of a stacked VTFET structure, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper VTFET of the stacked VTFET structure. The method also includes forming a first gate stack including a first gate dielectric layer and a first gate conductor layer surrounding a portion of the first semiconductor layer of the vertical fins. The method further includes forming a second gate stack including a second gate dielectric layer and a second gate conductor layer surrounding a portion of the second semiconductor layer of the vertical fins. The first gate conductor layer and the second gate conductor layer are the same material.
1. A method of forming a semiconductor structure, comprising:
forming one or more vertical fins each comprising a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor of a stacked vertical transport field-effect transistor structure, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper vertical transport field-effect transistor of the stacked vertical transport field-effect transistor structure;
forming a first bottom source/drain region of the lower vertical transport field-effect transistor;
forming a first gate stack comprising a first gate dielectric layer and a first gate conductor layer surrounding a portion of the first semiconductor layer of each of the one or more vertical fins above the first bottom source/drain region;
forming a first top source/drain region of the lower vertical transport field-effect transistor surrounding another portion of the first semiconductor layer of each of the one or more vertical fins above the first gate stack;
forming a second bottom source/drain region of the upper vertical transport field-effect transistor surrounding a portion of the second semiconductor layer of each of the one or more vertical fins above the first top source/drain region; and
forming a second gate stack comprising a second gate dielectric layer and a second gate conductor layer surrounding another portion of the second semiconductor layer of each of the one or more vertical fins above the second bottom source/drain region;
wherein the first gate conductor layer and the second gate conductor layer comprise a same material.
2. The method of claim 1 , wherein forming the first gate stack comprises utilizing a gate-first process and wherein forming the second gate stack comprises utilizing a gate-last process.
3. The method of claim 1 , wherein the first gate conductor layer is annealed and the second gate conductor layer is un-annealed.
4. The method of claim 3 , wherein the lower vertical transport field-effect transistor comprises an n-type field-effect transistor and the upper vertical transport field-effect transistor comprises a p-type field-effect transistor.
5. The method of claim 1 , wherein the first gate conductor layer comprises a given work function metal that is annealed and the second gate conductor layer comprises the given work function metal that is un-annealed.
6. The method of claim 5 , wherein the given work function metal comprises titanium nitride (TiN).
7. The method of claim 1 , further comprising performing a dopant drive-in at a same time for (i) the first bottom source/drain region of the lower vertical transport field-effect transistor, (ii) the first top source/drain region of the lower vertical transport field-effect transistor and (iii) the second bottom source/drain region of the upper vertical transport field-effect transistor.
8. The method of claim 1 , further comprising forming a second top source/drain region of the upper vertical transport field-effect transistor over a top of the second semiconductor layer of each of the one or more vertical fins.
9. A semiconductor structure, comprising:
one or more vertical fins each comprising a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor of a stacked vertical transport field-effect transistor structure, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper vertical transport field-effect transistor of the stacked vertical transport field-effect transistor structure;
a first bottom source/drain region of the lower vertical transport field-effect transistor;
a first gate stack comprising a first gate dielectric layer and a first gate conductor layer surrounding a portion of the first semiconductor layer of each of the one or more vertical fins above the first bottom source/drain region;
a first top source/drain region of the lower vertical transport field-effect transistor surrounding another portion of the first semiconductor layer of each of the one or more vertical fins above the first gate stack;
a second bottom source/drain region of the upper vertical transport field-effect transistor surrounding a portion of the second semiconductor layer of each of the one or more vertical fins above the first top source/drain region; and
a second gate stack comprising a second gate dielectric layer and a second gate conductor layer surrounding another portion of the second semiconductor layer of each of the one or more vertical fins above the second bottom source/drain region;
wherein the first gate conductor layer and the second gate conductor layer comprise a same material.
10. The semiconductor structure of claim 9 , wherein the first gate conductor layer is annealed and the second gate conductor layer is un-annealed.
11. The semiconductor structure of claim 10 , wherein the lower vertical transport field-effect transistor comprises an n-type field-effect transistor and the upper vertical transport field-effect transistor comprises a p-type field-effect transistor.
12. The semiconductor structure of claim 9 , wherein the first gate conductor layer comprises a given work function metal that is annealed and the second gate conductor layer comprises the given work function metal that is un-annealed.
13. The semiconductor structure of claim 12 , wherein the given work function metal comprises titanium nitride (TiN).
14. The semiconductor structure of claim 9 , further comprising a second top source/drain region of the upper vertical transport field-effect transistor over a top of the second semiconductor layer of each of the one or more vertical fins.
15. An integrated circuit comprising:
a stacked vertical transport field-effect transistor structure comprising:
one or more vertical fins each comprising a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor of the stacked vertical transport field-effect transistor structure, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper vertical transport field-effect transistor of the stacked vertical transport field-effect transistor structure;
a liner surrounding at least a portion of sidewalls of the isolation layer;
a first bottom source/drain region of the lower vertical transport field-effect transistor;
a first gate stack comprising a first gate dielectric layer and a first gate conductor layer surrounding a portion of the first semiconductor layer of each of the one or more vertical fins above the first bottom source/drain region;
a first top source/drain region of the lower vertical transport field-effect transistor surrounding another portion of the first semiconductor layer of each of the one or more vertical fins above the first gate stack;
a second bottom source/drain region of the upper vertical transport field-effect transistor surrounding a portion of the second semiconductor layer of each of the one or more vertical fins above the first top source/drain region; and
a second gate stack comprising a second gate dielectric layer and a second gate conductor layer surrounding another portion of the second semiconductor layer of each of the one or more vertical fins above the second bottom source/drain region;
wherein the first gate conductor layer and the second gate conductor layer comprise a same material.
16. The integrated circuit of claim 15 , wherein the first gate conductor layer is annealed and the second gate conductor layer is un-annealed.
17. The integrated circuit of claim 16 , wherein the lower vertical transport field-effect transistor comprises an n-type field-effect transistor and the upper vertical transport field-effect transistor comprises a p-type field-effect transistor.
18. The integrated circuit of claim 15 , wherein the first gate conductor layer comprises a given work function metal that is annealed and the second gate conductor layer comprises the given work function metal that is un-annealed.
19. The integrated circuit of claim 18 , wherein the given work function metal comprises titanium nitride (TiN).
20. The integrated circuit of claim 15 , further comprising a second top source/drain region of the upper vertical transport field-effect transistor over a top of the second semiconductor layer of each of the one or more vertical fins.