Semiconductor structure and fabrication method thereof
Semiconductor structure and method for fabricating a semiconductor structure are provided. A substrate including device regions and an isolation region located adjacent to and between the device regions is provided. A fin on the substrate, gate structures across the fin at the device regions, source/drain doped regions in the fin at two sides of each of the gate structures, and a sacrificial gate across the fin at the isolation region are provided. The sacrificial gate and a portion of the fin near a bottom of the sacrificial gate are removed, thus forming a first opening in the fin. An insulation structure in the first opening is formed. Two sides of the sacrificial gate are in contact with the source/drain doped regions at adjacent device regions. A top surface of the insulation structure is flush with or higher than top surfaces of the source/drain doped regions.
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate including device regions and an isolation region located adjacent to and between the device regions,
providing a fin on the substrate, gate structures across the fin at the device regions, source/drain doped regions in the fin at two sides of each of the gate structures, and a sacrificial gate across the fin at the isolation region;
removing the sacrificial gate and a portion of the fin near a bottom of the sacrificial gate, thus forming a first opening in the fin; and
forming an insulation structure in the first opening;
wherein:
the insulation structure includes a first insulation layer filling a bottom portion of the first opening, a second insulation layer conformally formed a top surface of the first insulation layer and sidewalls of the first opening exposed by the first insulation layer, and a third insulation layer filling up a trench formed by the second insulation layer;
two sides of the sacrificial gate are in contact with the source/drain doped regions at adjacent device regions; and
a top surface of the insulation structure is flush with or higher than top surfaces of the source/drain doped regions.
2. The method according to claim 1 , wherein the first opening has a dimension in a direction perpendicular to sidewalls of the gate structures in a range of approximately 20 nm to 34 nm.
3. The method according to claim 1 , wherein the first opening has a depth in a range of approximately 50 nm to 100 nm.
4. The method according to claim 1 , wherein the gate structures and the sacrificial gate are simultaneously formed, and each of the gate structures and the sacrificial gate includes a gate layer.
5. The method according to claim 4 , wherein, when the gate layer is made of a material including polysilicon, a process of forming the gate structures, the sacrificial gate, and the source/drain doping regions includes:
forming the gate structures across the fin at the device regions;
forming the sacrificial gate in the fin at the isolation region; and
forming the source/drain doped regions in the fin at both sides of each of the gate structures.
6. The method according to claim 4 , wherein, when the gate layer is made of a material including metal, a process of forming the gate structures, the sacrificial gate, and the source/drain doped regions includes:
forming dummy gate structures across the fin at the device regions and the isolated the region, respectively;
forming the source/drain doped regions in the fin at two sides of each of the dummy gate structures in the device regions, wherein the source/drain doped regions in the adjacent device regions are in contact with two sides of the dummy gate structure in the isolation region A, respectively;
forming a first dielectric layer on surfaces of the isolation structure and the source/drain doped regions, sidewalls and top surfaces of the fin, and sidewalls of the dummy gate structures;
removing the dummy gate structures, thus forming dummy gate openings in the first dielectric layer;
forming the gate structures in the dummy gate openings at the device regions; and
forming the sacrificial gate in the dummy gate opening at the isolation region.
7. The method according to claim 6 , wherein before the first opening is formed, the sacrificial gate is removed, and a second opening is formed in the first dielectric layer.
8. The method according to claim 7 , wherein:
the insulation structure fully fills the second opening; and
a process of forming the insulation structure includes:
forming the first insulation layer in the first opening, wherein the top surface of the first insulation layer is lower than a top surface of the substrate; and
forming the third insulation layer on the top surface of the first insulation layer, wherein the third insulation layer fully fills the first opening and the second opening.
9. The method according to claim 8 , wherein:
a process of forming the first insulation layer includes forming a first insulation material film in the first opening and the second opening, on surfaces of the first dielectric layer and the gate structures, and removing a portion of the first insulation material film, thus forming the first insulation layer;
the first insulation material film fully fills the first opening and the second opening;
the first insulation material film is made of a material including silicon oxide;
a process of forming the first insulation material film includes a fluid chemical vapor deposition process, or a physical vapor deposition process;
the third insulation layer is made of a material including silicon oxide; and
a process of forming the third insulation layer includes a fluid chemical vapor deposition process or a physical vapor deposition process.
10. The method according to claim 8 , wherein:
the first insulation layer has a dimension in a direction perpendicular to the surface of the substrate in a range of approximately 50 nm to 100 nm; and
the third insulation layer has a dimension in the direction perpendicular to the surface of the substrate in a range of approximately 40 nm to 90 nm.
11. The method according to claim 8 , wherein,
after forming the first insulation layer and before forming the third insulation layer, the method also includes forming the second insulation layer on the top surface of the first insulation layer and the sidewalls of the first opening and the second opening; and
the second insulation layer is made of a material including silicon nitride.
12. The method according to claim 11 , wherein the second insulation layer has a dimension in a direction perpendicular to the sidewalls of the gate structures in a range of approximately 3 nm to 9 nm.
13. The method according to claim 6 , wherein, after forming the insulation structure, the method also includes:
forming a second dielectric layer on surfaces of the first dielectric layer, the gate structures and the insulation structure;
removing a portion of the second dielectric layer, until top surfaces of the gate structures are exposed, thus forming a first contact hole in the second dielectric layer;
forming a first plug in the first contact hole;
removing a portion of the second dielectric layer and a portion of the first dielectric layer until top surfaces of the source/drain doped regions are exposed, thus forming second contact holes in the second dielectric layer; and
forming second plugs in the second contact holes.
14. The method according to claim 1 , wherein a bottom surface of the first opening is lower than bottom surfaces of the source/drain doped regions.
15. The method according to claim 14 , wherein the top surface of the first insulation layer is higher than the bottom surfaces of the source/drain doped regions.
16. The method according to claim 1 , wherein the second insulation layer is directly formed on the sidewalls of the first opening exposed by the first insulation layer.