Memory device and method for fabricating the same

1. A method for fabricating a memory device, comprising:

providing a substrate, wherein the substrate has a cell region and a peripheral region, and comprises a plurality of word lines and a plurality of isolation structures;

forming a silicon nitride layer on the substrate in the cell region;

forming a semiconductor layer on the substrate, wherein the silicon nitride layer is disposed between the substrate and the semiconductor layer;

patterning the semiconductor layer, the silicon nitride layer, and the substrate in the cell region to form a plurality of trenches, wherein the trenches expose portions of the substrate, and a bottom surface of each of the trenches is lower than a top surface of the substrate;

forming a doped-material layer on the semiconductor layer and filling the trenches;

removing a portion of the doped-material layer to form a plurality of contact portions, such that a top surface of each of the contact portions is aligned with, or lower than, a top surface of the semiconductor layer; and

forming a metal-stacking layer on the semiconductor layer, wherein the metal-stacking layer is disposed on the contact portions.

2. The method according to claim 1 , wherein before the step of depositing the doped-material layer on the semiconductor layer and filling the trenches, the method further comprises:

forming a stop layer on side walls of the trenches.

3. The method according to claim 2 , wherein a material of the stop layer comprises silicon nitride or silicon oxide.

4. The method according to claim 1 , wherein before the step of depositing the semiconductor layer on the substrate, the method further comprises:

forming a dielectric layer on the substrate in the peripheral region.

5. The method according to claim 4 , wherein the dielectric layer comprises a first dielectric layer and a second dielectric layer, and the second dielectric layer is thicker than the first dielectric layer.

6. The method according to claim 5 , further comprising:

doping the semiconductor layer in the peripheral region;

wherein the semiconductor layer on the first dielectric layer has a first conductivity type and the semiconductor layer on the second dielectric layer has a second conductivity type that is different than the first conductivity type.

7. The method according to claim 4 , wherein before the step of forming the dielectric layer on the substrate in the peripheral region, the method further comprises:

forming a silicon oxide layer on the substrate, wherein the silicon oxide layer in the cell region is disposed between the substrate and the silicon nitride layer; and

removing the silicon oxide layer in the peripheral region.

8. The method according to claim 1 , further comprising:

patterning the metal-stacking layer to form a plurality of bit lines on the contact portions and the semiconductor layer.

9. The method according to claim 8 , further comprising:

forming a capacitor contact and a capacitor between the bit lines.

10. The method according to claim 1 , wherein the metal-stacking layer comprises titanium, titanium nitride, tungsten, tungsten silicide, or tungsten nitride.

11. A memory device, comprising:

a substrate comprising a plurality of word lines and a plurality of isolation structures, wherein the substrate has a cell region and a peripheral region;

a silicon nitride layer disposed on the substrate in the cell region;

a non-doped semiconductor layer disposed on the silicon nitride layer, wherein the silicon nitride layer is disposed between the substrate and the non-doped semiconductor layer;

a plurality of contact portions adjacent to the non-doped semiconductor layer, wherein a bottom surface of each of the contact portions is lower than a top surface of the substrate; and

a metal-stacking layer disposed on the substrate, wherein a portion of the metal-stacking layer is disposed on the non-doped semiconductor layer and the contact portions.

12. The memory device according to claim 11 , further comprising:

a stop layer disposed between each of the contact portions and the non-doped semiconductor layer.

13. The memory device according to claim 12 , wherein a material of the stop layer comprises silicon nitride or silicon oxide.

14. The memory device according to claim 11 , wherein the memory device further comprises:

a dielectric layer disposed on the substrate in the peripheral region.

15. The memory device according to claim 14 , wherein the dielectric layer is divided into a first dielectric layer and a second dielectric layer, and the second dielectric layer is thicker than the first dielectric layer.

16. The memory device according to claim 15 , further comprising:

a first doped semiconductor layer disposed on the first dielectric layer; and

a second doped semiconductor layer disposed on the second dielectric layer;

wherein the first doped semiconductor layer has a first conductivity type and the second doped semiconductor layer has a second conductivity type that is different than the first conductivity type.

17. The memory device according to claim 16 , wherein the first conductivity type is P-type and the second conductivity type is N-type.

18. The memory device according to claim 16 , wherein another portion of the metal-stacking layer is disposed on the first doped semiconductor layer and the second doped semiconductor layer.

19. The memory device according to claim 14 , further comprising:

a silicon oxide layer disposed under the silicon nitride layer;

wherein the silicon oxide layer and the silicon nitride layer are disposed between the substrate and the non-doped semiconductor layer.

20. The memory device according to claim 11 , wherein the metal-stacking layer comprises titanium, titanium nitride, tungsten, tungsten silicide, or tungsten nitride.