Horizontal memory array structure with scavenger layer

1. A resistive random access memory (RRAM) device comprising:

a bit line overlying a semiconductor substrate;

a data storage layer around outer sidewalls and a top surface of the bit line;

a word line overlying the data storage layer;

a scavenger layer between the word line and the bit line, wherein a bottom surface of the scavenger layer is aligned with a bottom surface of the bit line, wherein a lateral thickness of the scavenger layer is less than a vertical thickness of the scavenger layer; and

an isolation structure overlying the bit line, wherein the data storage layer and the scavenger layer directly contact outer sidewalls of the isolation structure.

2. The RRAM device according to claim 1 , wherein the scavenger layer is configured to collect a reactive species from the data storage layer.

3. The RRAM device according to claim 1 , wherein a bottom surface of the word line extends below the top surface of the bit line, and wherein the data storage layer is disposed directly between the word line and the isolation structure.

4. The RRAM device according to claim 1 , wherein the scavenger layer is configured to direct a maximum electric field between the bit line and the word line to an upper region, the upper region is defined between the top surface of the bit line and an inner surface of the word line.

5. The RRAM device according to claim 4 , further comprising:

an outer scavenger layer directly between the data storage layer and the word line, wherein the outer scavenger layer comprises a same material as the scavenger layer.

6. The RRAM device according to claim 5 , wherein a top surface of the outer scavenger layer is above a top surface of the scavenger layer.

7. The RRAM device according to claim 1 , wherein the bit line and the word line each comprise tungsten, the scavenger layer comprises titanium nitride, and the data storage layer comprises hafnium oxide, titanium oxide, or tantalum oxide.

8. The RRAM device according to claim 1 , wherein a bottom surface of the isolation structure directly contacts the top surface of the bit line.

9. A memory device comprising:

a bit line overlying a substrate;

a word line overlying the bit line;

a data storage layer between the word line and the bit line, wherein a conductive filament is selectively formable within the data storage layer between the bit line and the word line; and

a scavenger layer between the word line and the bit line, wherein the scavenger layer is configured to confine the conductive filament to an upper region of the data storage layer such that the upper region is above a top surface of the bit line, wherein a vertical thickness of the scavenger layer is greater than a lateral thickness of the scavenger layer, wherein the lateral thickness is defined along a sidewall of the bit line, and wherein the vertical thickness is defined at a position vertically above the top surface of the bit line.

10. The memory device according to claim 9 , wherein the data storage layer extends from a bottom surface of the bit line to a point above the top surface of the bit line.

11. The memory device according to claim 9 , wherein the vertical thickness of the scavenger layer is at least 1.2 times greater than the lateral thickness of the scavenger layer.

12. The memory device according to claim 9 , wherein the scavenger layer is directly between the data storage layer and the bit line.

13. The memory device according to claim 12 , further comprising:

another scavenger layer between the data storage layer and the bit line, wherein the another scavenger layer is configured to confine the conductive filament to the upper region.

14. The memory device according to claim 13 , wherein outer sidewalls of the scavenger layer are laterally between outer sidewalls of the another scavenger layer.

15. The memory device according to claim 9 , further comprising:

a selector layer disposed between the word line and the bit line, wherein a maximum thickness of the selector layer is at least twice a maximum thickness of the data storage layer.

16. The memory device according to claim 9 , wherein the bit line and the word line comprise tungsten and the scavenger layer comprises titanium nitride.

17. A memory device comprising:

a first bit line overlying a substrate;

a second bit line overlying the first bit line;

a word line overlying the first and second bit lines;

a data storage layer between the word line and the first and second bit lines, wherein a first conductive filament is selectively formable within the data storage layer between the first bit line and the word line, and a second conductive filament is selectively formable within the data storage layer between the second bit line and the word line;

a first scavenger layer disposed between the word line and the first bit line, wherein a bottom surface of the first scavenger layer is aligned with a bottom surface of the data storage layer;

a second scavenger layer disposed between the word line and the second bit line, wherein a bottom surface of the second scavenger layer is disposed above a top surface of the first scavenger layer; and

wherein the first and second scavenger layers are configured to collect a reactive species from the data storage layer.

18. The memory device of claim 17 , further comprising:

a lower isolation structure disposed vertically between the first bit line and the second bit line; and

wherein the data storage layer extends continuously from opposing sidewalls of the first bit line, along opposing sidewalls of the lower isolation structure, to a point above the second scavenger layer.

19. The memory device of claim 17 , wherein the first scavenger layer continuously extends along opposing sidewalls of the first bit line and a top surface of the first bit line, wherein a lateral thickness of the first scavenger layer is less than a vertical thickness of the first scavenger layer.

20. The memory device of claim 17 , wherein outer opposing sidewalls of the first bit line are aligned with outer opposing sidewalls of the second bit line.