IP Library › Granted Patent US 11,140,784
Granted Patent B2
US 11,140,784 · App. 16/495,217 · Granted Oct 5, 2021

Printed wiring board and manufacturing method thereof

Inventors: Kohei Okamoto (Shiga, JP); Kousuke Miura (Shiga, JP); Hiroshi Ueda (Shiga, JP); Shoichiro Sakai (Osaka, JP); Maki Ikebe (Osaka, JP)
Assignees: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.; SUMITOMO ELECTRIC INDUSTRIES, LTD.
H05K3/108H05K1/0296H05K3/241H05K3/244H05K2201/0347H05K2203/072H05K2203/0723
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Quick Facts
Patent No.
US 11,140,784
App. No.
16/495,217
Granted
Oct 5, 2021
Kind
B2
Abstract

A printed wiring board includes a base film having insulation properties and a conductive pattern including multiple wiring portions laminated so as to run on at least one surface of the base film, wherein each wiring portion includes a first conductive portion and a second conductive portion coating an outer surface of the first conductive portion, wherein an average width of each wiring portion is 10 μm or greater to 50 μm or smaller, and an average thickness of the second conductive portion is 1 μm or greater to smaller than 8.5 μm. A method for manufacturing a printed wiring board includes a first conductive portion forming step of forming a first conductive portion forming each wiring portion by plating an opening of the resist pattern on the conductive foundation layer, a conductive foundation layer removing step, and a second conductive portion coating step.

Claims (21)

1. A printed wiring board comprising:

a base film having insulation properties; and

a conductive pattern including a plurality of wiring portions laminated so as to run on at least one surface of the base film,

wherein each wiring portion includes a first conductive portion and a second conductive portion coating an outer surface of the first conductive portion, the second conductive portion surrounding the first conductive portion,

wherein the first conductive portion has a tapered shape, in which an average width of the first conductive portion increases in a direction from an upper surface of the first conductive portion to a bottom surface of the first conductive portion,

wherein a ratio of an average width of an upper surface of each wiring portion relative to an average width of a bottom surface of each wiring portion is 0.9 to 1.3, and

wherein an average width of each wiring portion is 10 μm or greater to 50 μm or smaller, and an average thickness of the second conductive portion is 1 μm or greater to smaller than 8.5 μm.

2. The printed wiring board according to claim 1 ,

wherein an average interval of each wiring portion is 3 μm or greater to 20 μm or smaller.

3. The printed wiring board according to claim 1 ,

wherein a ratio of the average width of the upper surface of the first conductive portion to the average width of the bottom surface of the first conductive portion is 0.5 or greater to smaller than 1.0.

4. A printed wiring board according to claim 1 ,

wherein a ratio of an average height of each wiring portion to an average height of the first conductive portion is 1.05 or greater to 5 or smaller.

5. The printed wiring board according to claim 1 , wherein each wiring portion substantially has a non-tapered shape, in which the average width of each wiring portion is substantiality the same through the upper surface of each wiring portion and the bottom surface of each wiring portion.

6. The printed wiring board according to claim 1 ,

wherein the first conductive portion has a pair of side surfaces, and the second conductive portion is laminated on each of the pair of side surfaces.

7. The printed wiring board according to claim 1 ,

wherein the first conductive portion has a pair of side surfaces and a top surface continuously formed from the pair of side surfaces, and

wherein the second conductive portion is laminated on each of the pair of side surfaces and the top surface.

8. The printed wiring board according to claim 1 ,

wherein the first conductive portion includes a conductive foundation layer laminated on the at least one surface of the base film, and an average thickness of the conductive foundation layer is 50 nm or greater to 2 μm or smaller.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2019
From: OKAMOTO, KOHEI; MIURA, KOUSUKE; UEDA, HIROSHI; SAKAI, SHOICHIRO; IKEBE, MAKI
To: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.; SUMITOMO ELECTRIC INDUSTRIES, LTD.
Reel/Frame 050416/0052 →
Priority Claims (1)
JP JP2017-097663 · May 16, 2017 · national
Continuity (1)
Related Publication 20200022262A1 · Jan 16, 2020