Method and apparatus for digital only secure test mode entry

1. An integrated circuit, comprising:

a digital non-resettable state retention storage circuit connected to store an authentication control pattern for authorizing test mode access to a secure circuit;

a digital safety interlock gate circuit connected to store a safety interlock gate setting that may be accessed independently from a test mode enable signal; and

combinatorial logic circuitry for generating the test mode enable signal only when the safety interlock gate setting is set to a first value and the digital non-resettable state retention storage circuit stores the authentication control pattern.

2. The integrated circuit of claim 1 , where the digital non-resettable state retention storage circuit comprises a plurality of non-resettable storage elements connected to store the authentication control pattern for authorizing test mode access to the secure circuit.

3. The integrated circuit of claim 2 , where the plurality of non-resettable storage elements comprises a plurality of non-resettable flip-flop storage devices.

4. The integrated circuit of claim 3 , where the plurality of non-resettable flip-flop storage devices are connected to load the authentication control pattern in response to successful authentication by authentical logic.

5. The integrated circuit of claim 1 , where the digital safety interlock gate circuit comprises one or more digital resettable storage elements for storing the safety interlock gate setting.

6. The integrated circuit of claim 1 , where the combinatorial logic circuitry comprises a logical AND gate connected to receive the safety interlock gate setting and a match signal derived from the digital non-resettable state retention storage circuit to generate the test mode enable signal only.

7. The integrated circuit of claim 1 , where the digital non-resettable state retention storage circuit is configured to store the authentication control pattern through device reset events but not through device power down events.

8. A test control method comprising:

performing, by a test control device, an admissions control process to authorize test mode access to a secure circuit in an integrated circuit device;

generating an authentication control pattern in response to authorizing test mode access to the secure circuit in the integrated circuit device;

storing the authentication control pattern in a digital non-resettable state retention storage circuit at the test control device; and

generating, by the test control device, a test mode enable signal with combinatorial logic circuitry which detects when the digital non-resettable state retention storage circuit stores the authentication control pattern.

9. The test control method of claim 8 , where performing the admissions control process occurs during power up mode of the integrated circuit device.

10. The test control method of claim 8 , where performing the admissions control process comprises performing a challenge-response process or receiving a certificate or password.

11. The test control method of claim 8 , further comprising:

receiving, at the test control device, a test mode safety signal; and

storing the test mode safety signal at a safety interlock gate that may be accessed independently from the test mode enable signal.

12. The test control method of claim 11 , where the safety interlock gate comprises one or more digital resettable storage elements for storing the test mode safety signal.

13. The test control method of claim 11 , where generating the test mode enable signal comprises using the combinatorial logic circuitry to generate the test mode enable signal only when both the digital non-resettable state retention storage circuit stores the authentication control pattern and the safety interlock gate stores the test mode safety signal that is set to a first value.

14. The test control method of claim 8 , where storing the authentication control pattern comprises storing the authentication control pattern in a plurality of non-resettable storage elements connected to store the authentication control pattern for authorizing test mode access to the secure circuit.

15. The test control method of claim 14 , where storing the authentication control pattern comprises sequentially loading the plurality of non-resettable storage devices with the authentication control pattern in response to successful authentication by authentical logic.

16. The test control method of claim 8 , further comprising resetting the digital non-resettable state retention storage circuit to remove the authentication control pattern at a power down event but not at a device reset event.

17. A fully digital test control access system for an integrated circuit, comprising:

a secure unit comprising one or more logic elements that are protected from test access during normal operation;

test circuitry connected to the one or more logic elements, wherein the test circuitry is configured to provide test access to the one or more logic elements in response to a test mode enable signal; and

test control access circuitry connected to authorize and enable test access by the test circuitry to the secure unit, the test control access circuitry comprising:

a digital non-resettable state retention storage circuit for storing an authentication control pattern which is generated in response to authorized test mode access to the secure unit; and

combinatorial logic circuitry for generating the test mode enable signal when the digital non-resettable state retention storage circuit stores the authentication control pattern.

18. The fully digital test control access system of claim 17 , where the secure unit comprises a plurality of logic elements connected in a scan chain to receive test access from the test circuitry during test operation.

19. The fully digital test control access system of claim 18 , where the test circuitry comprises a plurality of scan flip-flops connected in a chain to provide test access to the one or more logic elements.

20. The fully digital test control access system of claim 17 , where the digital non-resettable state retention storage circuit comprises a plurality of non-resettable storage flip-flop devices connected to load the authentication control pattern in response to successful authentication by authentical logic.

21. The fully digital test control access system of claim 17 , further comprising a digital safety interlock gate circuit connected to store a safety interlock gate setting that may be accessed independently from the test mode enable signal.