Semiconductor device with integrated capacitor and manufacturing method thereof

1. A method of manufacturing a semiconductor structure, the method comprising:

providing a substrate;

forming a first conductive layer having a first opening over the substrate;

depositing a first dielectric layer over the first conductive layer and covering the first opening;

forming a second conductive layer having a second opening over the first dielectric layer;

depositing a second dielectric layer over the second conductive layer and covering the second opening;

performing an etching operation through the second dielectric layer at the second opening and the first dielectric layer at the first opening to form a first via; and

forming a first conductive structure in the first via.

2. The method according to claim 1 , further comprising forming a redistribution layer over the substrate prior to forming the first conductive layer, wherein the first conductive structure is in physical contact with the redistribution layer.

3. The method according to claim 1 , prior to depositing the second conductive layer, further comprising:

forming a third conductive layer having a third opening adjacent to the first conductive layer; and

depositing a third dielectric layer over the first conductive layer and covering the third opening.

4. The method according to claim 3 , wherein the first dielectric layer comprises an upper surface, and the third opening exposes the upper surface of the first dielectric layer.

5. The method according to claim 3 , wherein the third dielectric layer covers the first opening and the etching operation runs through the third dielectric layer.

6. The method according to claim 3 , wherein the second dielectric layer fills the second opening.

7. The method according to claim 6 , further comprising:

performing another etching operation through the second dielectric layer and the third dielectric layer at the third opening to thereby form a second via; and

forming a second conductive structure in the second via.

8. The method according to claim 1 , wherein the second conductive layer comprises a sidewall and an upper surface, wherein the etching operation exposes the sidewall and the upper surface of the second conductive layer, and the first conductive structure is in contact with the sidewall and the upper surface of the second conductive layer.

9. The method according to claim 1 , wherein the second opening overlaps the first opening and has a first width, and the first opening has a second width less than the first width.

10. The method according to claim 1 , wherein the first conductive layer comprises a sidewall, the first dielectric layer comprises a portion on the sidewall, and after the etching operation the portion of the first dielectric layer is left on the sidewall of the first conductive layer.

11. The method according to claim 1 , wherein the first dielectric layer and the second dielectric layer are formed of a same material.

12. The method according to claim 1 , wherein the first conductive layer and the second conductive layer are electrically connected through the first conductive structure.

13. A method of manufacturing a semiconductor structure, the method comprising:

providing a substrate;

forming a first conductive layer over the substrate, the first conductive layer comprising a first opening;

depositing a first dielectric layer over the first conductive layer and within the first opening;

forming a second conductive layer over the first dielectric layer and the first conductive layer, the second conductive layer comprising a second opening laterally spaced apart from the first opening;

forming a second dielectric layer over the second conductive layer, the first dielectric layer and the first conductive layer;

forming a first via through the second dielectric layer and the first dielectric layer at the first opening; and

forming a second via through the second dielectric layer at the second opening and the first dielectric layer.

14. The method according to claim 13 , wherein the first via and the second via are formed by a dry etching operation.

15. The method according to claim 13 , wherein the first conductive layer forms a capacitor with the second conductive layer.

16. The method according to claim 13 , wherein second conductive layer comprises an upper surface and a sidewall, and wherein the forming of the second via exposes the upper surface and the sidewall of the second conductive layer.

17. The method according to claim 13 , wherein the first conductive layer and the second conductive layer comprises titanium nitride.

18. The method according to claim 13 , wherein the first dielectric layer is deposited over the first conductive layer in a conformal manner.

19. The method according to claim 13 , wherein the first via comprises a stepped shape.

20. A method of manufacturing a semiconductor structure, the method comprising:

forming a patterned first conductive layer over a substrate, wherein the patterned first conductive layer comprises a planar upper surface and defines a first opening;

depositing a first dielectric layer over the first patterned conductive layer and within the first opening;

forming a patterned second conductive layer over the first dielectric layer, wherein the patterned second conductive layer comprises a planar upper surface and defines a second opening;

depositing a second dielectric layer over the second patterned conductive layer and within the second opening;

forming a patterned third conductive layer over the second dielectric layer, wherein the patterned third conductive layer comprises a planar upper surface and defines a third opening overlapping the first opening;

forming a third dielectric layer over the third patterned conductive layer;

forming a first via through the first patterned conductive layer at the first opening and the third patterned conductive layer at the third opening, the first via exposing the planar upper surface of the first patterned conductive layer and the planar upper surface of the third patterned conductive layer;

forming a second via through the second patterned conductive layer at the second opening and the third dielectric layer, the second via exposing the planar upper surface of the second patterned conductive layer, and

forming a first conductive structure and a second conductive structure in the first via and the second via, respectively.