IP Library Granted Patent US 11,145,814
Granted Patent B2
US 11,145,814 · App. 16/538,262 · Granted Oct 12, 2021

Phase change memory with conductive bridge filament

Inventors: Nanbo Gong (White Plains, NY); Takashi Ando (Tuckahoe, NY); Guy M. Cohen (Ossining, NY)
Assignee: International Business Machines Corporation
H01L45/1286H01L27/2427H01L45/06H01L45/1233H01L45/1246H01L45/1608H01L45/144
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Quick Facts
Patent No.
US 11,145,814
App. No.
16/538,262
Granted
Oct 12, 2021
Kind
B2
Abstract

Methods and structures for fabricating a semiconductor device that includes a reduced programming current phase change memory (PCM) are provided. The method includes forming a bottom electrode. The method further includes forming a PCM and forming a conductive bridge filament in a dielectric to serve as a heater for the PCM. The method also includes forming a top electrode.

Claims (33)

1. A semiconductor device including a reduced programming current phase change memory (PCM), comprising:

a bottom electrode;

a deposited conductive bridge filament centrally positioned on the bottom electrode; and

a pillar PCM device stack positioned on the conductive bridge filament, with the pillar PCM device stack including a PCM layer and a top electrode.

2. The semiconductor device of claim 1 , wherein the conductive bridge filament is formed during operation of the semiconductor device.

3. The semiconductor device of claim 1 , further comprising:

spacers around the PCM device stack; and

contacts connecting the top electrode.

4. The semiconductor device of claim 1 , wherein a reset current of the PCM is less than a current of low resistance state of a conductive bridging random access memory (CBRAM) dielectric.

5. The semiconductor device of claim 1 , wherein the PCM includes a critical dimension larger than a size of a conductive bridging random access memory (CBRAM) dielectric.

6. A semiconductor device including a reduced programming current phase change memory (PCM), comprising:

a bottom contact;

a reduced size bottom electrode;

a conductive bridge filament in a silicon oxide (SiO 2 ) dielectric positioned on the reduced size bottom electrode;

a PCM, wherein the reduced size bottom electrode is connected to the PCM by the conductive bridge filament, with a top planar surface of the reduced size bottom electrode having an area equal to a bottom planar surface of the SiO 2 dielectric and a smaller area than a bottom planar surface of the PCM; and

a top electrode.

7. The semiconductor device of claim 6 , wherein the conductive bridge filament is formed during operation of the semiconductor device.

8. The semiconductor device of claim 7 , wherein the PCM is one of a mushroom cell and a pillar cell.

9. The semiconductor device of claim 8 , wherein the PCM includes a critical dimension larger than a size of a conductive bridging random access memory (CBRAM) dielectric.

10. The semiconductor device of claim 7 , wherein a reset current of the PCM is less than a current of low resistance state of a conductive bridging random access memory (CBRAM) dielectric.

11. The semiconductor device of claim 6 , further comprising:

spacers around the PCM; and

contacts connecting the top electrode.

12. A semiconductor device including a reduced programming current phase change memory (PCM), comprising:

a bottom electrode;

a deposited conductive bridge filament centrally positioned on the bottom electrode; and

a PCM device stack, including a PCM layer and a top electrode, positioned on the conductive bridge filament, with spacers around the PCM device stack.

13. The semiconductor device of claim 12 , wherein the conductive bridge filament is formed during operation of the semiconductor device.

14. The semiconductor device of claim 13 , wherein the PCM is one of a mushroom cell and a pillar cell.

15. The semiconductor device of claim 12 , further comprising:

contacts connecting the top electrode.

16. The semiconductor device of claim 12 , wherein a reset current of the PCM is less than a current of low resistance state of a conductive bridging random access memory (CBRAM) dielectric.

17. The semiconductor device of claim 12 , wherein the PCM includes a critical dimension larger than a size of a conductive bridging random access memory (CBRAM) dielectric.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 12, 2019
From: GONG, NANBO; ANDO, TAKASHI; COHEN, GUY M.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 050027/0421 →
Continuity (1)
Related Publication 20210050518A1 · Feb 18, 2021
Cited By (1)
US 12,310,265