Memory device and manufacturing method thereof
A memory device includes a conductive wire, a first 2-D material layer, a phase change element, and a top electrode. The first 2-D material layer is over the conductive wire. The phase change element extends along a surface of the first 2-D material layer distal to the conductive layer. The top electrode is over the phase change element.
1. A memory device, comprising:
a conductive wire;
a dielectric layer over the conductive wire;
a bottom electrode in the dielectric layer over the conductive wire, wherein a bottom surface of the bottom electrode is level with a bottom surface of the dielectric layer;
a first 2-D material layer over and in contact with the bottom electrode, wherein the first 2-D material layer vertically overlaps an entirety of the bottom electrode;
a phase change element spaced from the conductive wire at least in part by the first 2-D material layer; and
a top electrode over the phase change element.
2. The memory device of claim 1 , further comprising:
a bottom electrode between the conductive wire and the first 2-D material layer.
3. The memory device of claim 1 , wherein the phase change element has a sidewall extending upwards from a surface of the first 2-D material layer distal to the conductive wire.
4. The memory device of claim 1 , wherein a surface of the phase change element proximal to the conductive wire extends along a surface of the first 2-D material layer distal to the conductive wire.
5. The memory device of claim 1 , further comprising:
a second 2-D material layer between the phase change element and the top electrode.
6. The memory device of claim 5 , wherein the first 2-D material layer is narrower than the second 2-D material layer.
7. The memory device of claim 5 , wherein the second 2-D material layer extends along a surface of the phase change element distal to the conductive wire.
8. The memory device of claim 5 , wherein the second 2-D material layer overlaps an entirety of a surface of the phase change element distal to the conductive wire.
9. The memory device of claim 1 , further comprising:
a dielectric layer laterally surrounding the phase change element and the first 2-D material layer.
10. A memory device, comprising:
a conductive wire;
a bottom electrode over the conductive wire;
a phase change element over the bottom electrode;
a first 2-D material layer over the phase change element;
a second 2-D material layer between the phase change element and the bottom electrode, wherein a width of the second 2-D material layer is equal to a maximum width of the bottom electrode; and
a top electrode spaced from the phase change element at least in part by the first 2-D material layer.
11. The memory device of claim 10 , wherein the first 2-D material layer has a width greater than a width of a bottommost portion of the phase change element.
12. The memory device of claim 10 , further comprising:
an inter-metal dielectric (IMD) layer laterally surrounding the phase change element, wherein the first 2-D material layer is in contact with a surface of the IMD layer.
13. The memory device of claim 10 , wherein a sidewall of the top electrode, a sidewall of the phase change element, and a sidewall of the first 2-D material layer are vertically aligned.
14. A memory device, comprising:
a first transistor and a second transistor over a substrate;
a first conductive wire over and electrically connected to the first transistor;
a second conductive wire over and electrically connected to the second transistor;
a dielectric layer over the first and second conductive wires;
a bottom electrode in the dielectric layer and in contact with the first conductive wire, wherein a top surface of the bottom electrode is lower than a top surface of the dielectric layer;
a conductive via in the dielectric layer and in contact with the second conductive wire, wherein a top surface of the conductive via is level with the top surface of the dielectric layer;
a first 2-D material layer disposed on the bottom electrode;
a phase change element over the first 2-D material layer, wherein the phase change element is separated from the bottom electrode by the first 2-D material layer;
a second 2-D material layer over the phase change element; and
a top electrode over the second 2-D material layer, wherein the top electrode is separated from the phase change element by the second 2-D material layer.
15. The memory device of claim 14 , wherein the dielectric layer is in contact with the bottom electrode and the phase change element.
16. The memory device of claim 15 , wherein the phase change element has an upper portion over a top surface of the dielectric layer, the upper portion is wider than a lower portion of the phase change element, and the second 2-D material layer is in contact with the upper portion of the phase change element.
17. The memory device of claim 14 , wherein the first 2-D material layer is narrower than the second 2-D material layer.
18. The memory device of claim 14 , wherein the bottom electrode comprises an electrode layer and a diffusion barrier surrounding the electrode layer, the first 2-D material layer is in contact with the electrode layer and the diffusion barrier.
19. The memory device of claim 14 , further comprising an inter-metal dielectric (IMD) layer laterally surrounding the phase change element, wherein the second 2-D material layer is in contact with the IMD layer.
20. The memory device of claim 19 , wherein a sidewall of the phase change element is in contact with the IMD layer.