Wideband amplifier circuit

1. A circuit comprising:

a first coil coupled to an input node;

first and second transistors;

a second coil having a first terminal coupled to a source terminal of the first transistor, and a second terminal coupled to a source terminal of the second transistor;

a first capacitor coupled between a ground node and the first terminal of the second coil, and a second capacitor coupled between the ground node and the second terminal of the second coil; and

a third coil having a first terminal coupled to a gate terminal of the first transistor, a second terminal coupled to a gate terminal of the second transistor;

wherein, responsive to receiving an input signal, the first coil is configured to be electromagnetically convey the input signal to the second and third coils.

2. The circuit of claim 1 , further comprising a reference voltage generator circuit, wherein the reference voltage generator circuit is coupled to a center tap of the third coil.

3. The circuit of claim 1 , wherein the second coil further includes a center tap coupled to a ground node.

4. The circuit of claim 1 , further comprising a third capacitor coupled between first and second terminals of the first coil.

5. The circuit of claim 1 , wherein the circuit comprises a common-gate amplifier configured to receive a single-ended input signal and provide a differential output signal.

6. The circuit of claim 1 , wherein the circuit comprises a common-gate amplifier configured to receive a differential input signal and provide a differential output signal.

7. The circuit of claim 1 , wherein the circuit comprises a non-inverting gain amplifier.

8. The circuit of claim 1 , wherein the first coil is implemented on a first metal layer of an integrated circuit die, wherein the second coil is implemented on a second metal layer of the integrated circuit die, and wherein the third coil is implemented on a third metal layer of the integrated circuit die.

9. The circuit of claim 8 , wherein respective source terminals of the first and second transistors are second metal layer of the integrated circuit die, and wherein gate terminal of the first and second transistors are coupled to the third metal layer of the integrated circuit die.

10. A method comprising:

receiving an input signal at a first coil of an amplifier circuit;

electromagnetically conveying the input signal to second and third coils of the amplifier circuit, wherein the second coil is coupled between a source terminal of a first transistor and a source terminal of a second transistor, the source terminals of the first and second transistors being capacitively coupled to ground by first and second capacitors, respectively, and wherein the third coil is coupled between respective gate terminals of the first and second transistors; and

providing an output signal on respective drain terminals of the first and second transistors, wherein the output signal is an amplified version of the input signal.

11. The method of claim 10 , wherein receiving the input signal comprises receiving a single-ended signal, and wherein providing the output signal comprises providing a differential signal.

12. The method of claim 10 , wherein receiving the input signal comprises receiving a first differential signal, and wherein providing the output signal comprises providing a second differential signal.

13. The method of claim 10 , further comprising a voltage generation circuit providing a DC bias voltage to a center tap of the third coil.

14. The method of claim 10 , further comprising the amplifier circuit providing the output signal at the same polarity with respect to an input signal provided to an input circuit.

15. An integrated circuit comprising:

an amplifier circuit including:

a first coil implemented on a first metal layer;

a second coil implemented on a second metal layer;

a first capacitor coupled between a ground node and a first terminal of the second coil;

a second capacitor coupled between the ground node and the second terminal of the second coil;

a third coil implemented on a third metal layer;

a first transistor having a gate terminal coupled to the third coil, a source terminal coupled to the second coil, and a drain terminal coupled to a first output node; and

a second transistor having a gate terminal coupled to the third coil, a source terminal coupled to the second coil, and a drain terminal coupled to a second output node;

wherein responsive to receiving an input signal, the first coil is configured to electromagnetically convey the input signal to the second and third coils.

16. The integrated circuit as recited in claim 15 , wherein the amplifier circuit is configured to provide a differential output signal on the first and second output nodes.

17. The integrated circuit as recited in claim 15 , wherein the amplifier circuit is configured to receive a single-ended input signal and provide a differential output signal.

18. The integrated circuit as recited in claim 15 , wherein the amplifier circuit is configured to receive a differential input signal and provide a differential output signal.

19. The integrated circuit as recited in claim 15 , wherein the amplifier circuit further includes a voltage generation circuit configured to provide a DC bias voltage on a center tap of the third coil.

20. The integrated circuit as recited in claim 15 , wherein the amplifier circuit is coupled between an upconversion circuit and antenna, wherein the amplifier circuit is configured to amplify and transmit, via the antenna, a radio frequency signal received from the upconversion circuit.