IP Library › Granted Patent US 11,153,123
Granted Patent B2
US 11,153,123 · App. 16/688,866 · Granted Oct 19, 2021

System and method for providing first arrival path (FAP) and delay spread estimation (DSE) in wireless communication system

Inventors: Bofeng Yuan (Carlsbad, CA); Hongbing Cheng (San Diego, CA); Kee-Bong Song (San Diego, CA)
Assignee: Samsung Electronics Co., Ltd.
H04L25/0216H04B1/7113H04B17/336H04L25/022H04L25/0256
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Quick Facts
Patent No.
US 11,153,123
App. No.
16/688,866
Granted
Oct 19, 2021
Kind
B2
Abstract

A method for minimizing a time domain mean square error (MSE) of channel estimation (CE) includes estimating, by a processor, a power delay profile (PDP) from a time domain observation of reference signal (RS) channels; estimating, by the processor, a noise variance of the RS channels; and determining, by the processor, a first arrival path (FAP) value and a delay spread estimation (DSE) value based on the estimated PDP and the estimated noise variance for minimizing the MSE of CE.

Claims (446)

1. A method for minimizing a time domain mean square error (MSE) of channel estimation (CE), the method comprising:

estimating, by a processor, a power delay profile (PDP) from a time domain observation of reference signal (RS) channels;

estimating, by the processor, a noise variance of the RS channels;

determining, by the processor, a first arrival path (FAP) value and a delay spread estimation (DSE) value based on the estimated PDP and the estimated noise variance; and

determining, by the processor, a minimum value of the time domain MSE based on the estimated PDP, the estimated noise variance, and a length of an uniform PDP.

2. A method for minimizing a time domain mean square error (MSE) of channel estimation (CE), the method comprising:

estimating, by a processor, a power delay profile (PDP) from a time domain observation of reference signal (RS) channels;

estimating, by the processor, a noise variance of the RS channels; and

determining, by the processor, a first arrival path (FAP) value and a delay spread estimation (DSE) value based on the estimated PDP and the estimated noise variance for minimizing the MSE of CE, wherein the time domain MSE is:

MSE

=

1

+

L

⁢

σ

2

(

1

+

L

⁢

σ

2

)

2

+

[

1

(

1

+

L

⁢

σ

2

)

2

-

2

1

+

L

⁢

σ

2

]

⁢

∑

i

=

F

L

+

F

-

1

⁢

⁢

P

i

(

1

)

wherein F and L are integers, where:

1

≤

L

≤

3

⁢

N

4

,

-

N

4

≤

F

≤

N

4

.

wherein, σ 2 is the noise variance, P i is power of an i-th channel tap or an uniform PDP, F is an index of the FAP, N is a length of the estimated PDP, and L is a length of the uniform PDP.

3. The method of claim 2 , wherein determining the FAP value and the DSE value to minimize the time domain MSE comprises determining, by the processor, a value of F and a value of L, wherein a minimum value of the time domain MSE is determined based on the value of F and the value of L.

4. The method of claim 3 , wherein the value of L is the delay spread value for minimizing the MSE and the estimated noise variance is capped at a signal to noise ratio (SNR)=20 dB.

5. The method of claim 3 , wherein the determining the value of F and the value of L for minimizing the time domain MSE comprises:

assigning, by the processor, a value “0” to the index of the FAP F;

determining, by the processor, a minimized value of MSE and corresponding value of L for each F of a plurality of F values within and

-

N

4

≤

F

<

0

⁢

⁢

and

⁢

⁢

0

<

F

≤

N

4

;

determining, by the processor, the value of F and the value of L based on comparing minimized values of MSE for the plurality of F values within

-

N

4

≤

F

<

0

⁢

⁢

and

⁢

⁢

0

<

F

≤

N

4

.

6. The method of claim 5 , wherein the value of F and the value of L correspond to the minimum value of the time domain MSE from among the minimized values of MSE for the plurality of F values within

-

N

4

≤

F

<

0

⁢

⁢

and

⁢

⁢

0

<

F

≤

N

4

,

wherein the minimized values of MSE and the corresponding values of L are determined using equation (1).

7. The method of claim 5 , further comprising stopping a search of the value of F and the value of L for F >0 or F<0, by the processor, in response to the minimized value of MSE, for F within

-

N

4

≤

F

<

0

⁢

⁢

or

⁢

⁢

0

<

F

≤

N

4

,

being increased as |F| increased for n consecutive times, wherein the n is 5.

8. The method of claim 5 , further comprising scaling, by the processor, the value of F and the value of L based on a difference of sampling time between the RS channels and data resource elements (REs) to determine a scaled value of F and a scaled value of L.

9. The method of claim 8 , wherein the scaled value of F is F′, wherein F′=scaling factor×F, and the scaled value of L is L′, wherein L′=scaling factor×L, wherein

scaling

⁢

⁢

factor

=

Sample

⁢

⁢

duration

⁢

⁢

of

⁢

⁢

RS

⁢

⁢

PDP

Sample

⁢

⁢

duration

⁢

⁢

of

⁢

⁢

data

⁢

⁢

REs

=

N

IFFT

×

Δ

⁢

⁢

f

N

PDP

×

Δ

⁢

⁢

f

×

12

ρ

wherein N IFFT is a size of Fast Fourier Transform (FFT), N PDP is a length of the estimated PDP, Δf is a subcarrier spacing, and p is a density of RS REs.

10. The method of claim 9 , wherein the method further comprising:

determining, by the processor, CE and a frequency correlation between the RS channels and the data REs, based on F′ and L′.

11. A system for minimizing a time domain mean square error (MSE) of channel estimation (CE), the system comprising:

a memory and a processor in communication with the memory, wherein the processor is configured to:

estimate a power delay profile (PDP) from time domain observation of reference signal (RS) channels;

estimate a noise variance of the RS channels;

determine a first arrival path (FAP) value and a delay spread estimation (DSE) value based on the estimated PDP and the estimated noise variance; and

determine a minimum value of the time domain MSE based on the estimated PDP, the estimated noise variance, and a length of an uniform PDP.

12. The system of claim 11 , wherein the time domain MSE is:

MSE

=

1

+

L

⁢

σ

2

(

1

+

L

⁢

σ

2

)

2

+

[

1

(

1

+

L

⁢

σ

2

)

2

-

2

1

+

L

⁢

σ

2

]

⁢

∑

L

+

F

-

1

i

=

F

⁢

P

i

(

1

)

wherein F and L are integers, where:

1

≤

L

≤

3

⁢

N

4

,

⁢

-

N

4

≤

F

≤

N

4

.

wherein, σ 2 is the noise variance, P i is power of an i-th channel tap or the uniform PDP, F is an index of the FAP, N is a length of the estimated PDP, and L is the length of the uniform PDP.

13. The system of claim 12 , wherein the processor is further configured to:

determine the FAP value and the DSE value to minimize the time domain MSE based on determining a value of F and a value of L, wherein the processor is further configured to determine the minimum value of the time domain MSE based on the value of F and the value of L.

14. The system of claim 13 , wherein the value of L is the delay spread value for minimizing the MSE and the estimated noise variance is capped at a signal to noise ratio (SNR)=20 dB.

15. The system of claim 13 , wherein the processor is further configured to:

assign a value “0” to the index of the FAP F;

determine a minimized value of MSE and corresponding value of L for each F of a plurality of F values within arm

-

N

4

≤

F

<

0

⁢

⁢

and

⁢

⁢

0

<

F

≤

N

4

;

determine the value of F and the value of L based on comparing minimized values of MSE for the plurality of F values within

-

N

4

≤

F

<

0

⁢

⁢

and

⁢

⁢

0

<

F

≤

N

4

.

16. The system of claim 15 , wherein the value of F and the value of L correspond to the minimum value of the time domain MSE from among the minimized values of MSE for the plurality of F values within

-

N

4

≤

F

<

0

⁢

⁢

and

⁢

⁢

0

<

F

≤

N

4

,

wherein the minimized values of MSE and the corresponding values of L are determined using equation (1).

17. The system of claim 15 , wherein the processor is further configured to stop a search of the value of F and the value of L for F >0 or F<0, by the processor, in response to the minimized value of MSE, for F within

-

N

4

≤

F

<

0

⁢

⁢

and

⁢

⁢

0

<

F

≤

N

4

,

being increased as |F| increased for n consecutive times, wherein the n is 5.

18. The system of claim 15 , wherein the processor is further configured to scale the value of F and the value of L based on a difference of sampling time between RS channels and data resource elements (REs) to determine a scaled value of F and a scaled value of L.

19. The system of claim 18 , wherein the scaled value of F is F′, wherein F′=scaling factor×F, and the scaled value of L is L′, wherein L′=scaling factor×L, wherein

scaling

⁢

⁢

factor

=

Sample

⁢

⁢

duration

⁢

⁢

of

⁢

⁢

RS

⁢

⁢

PDP

Sample

⁢

⁢

duration

⁢

⁢

of

⁢

⁢

data

⁢

⁢

REs

=

N

IFFT

×

Δ

⁢

⁢

f

N

PDP

×

Δ

⁢

⁢

f

×

12

ρ

wherein N IFFT is a size of Fast Fourier Transform (FFT), N PDP is a length of the estimated PDP, Δf is a subcarrier spacing, and p is a density of RS REs.

20. The system of claim 19 , wherein the processor is further configured to determine CE and a frequency correlation between RS channels and data REs, based on F′ and L′.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2020
From: YUAN, BOFENG; CHENG, HONGBING; SONG, KEE-BONG
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 052938/0031 →
Continuity (2)
Provisional Application 62888827 · Aug 19, 2019
Related Publication 20210058273A1 · Feb 25, 2021