Channel circuit of source driver
A channel circuit of a source driver, including a first digital-to-analog converter (DAC), a second DAC, a first switch, a second switch and an output buffer circuit, is provided. The output terminal of the output buffer circuit is configured to be coupled to a data line of a display panel. An output terminal of the first DAC is coupled to a first input terminal among the input terminals of the output buffer circuit. An output terminal of the second DAC is coupled to a second input terminal among the input terminals of the output buffer circuit. The first switch is disposed along a first signal path between the output terminal of the first DAC and the output terminal of the output buffer circuit. The second switch is disposed along a second signal path between the output terminal of the second DAC and the output terminal of the output buffer circuit.
1. A source driver, comprising:
a plurality of channel circuits, each of the channel circuits comprising:
an output buffer circuit, having a first input terminal, a second input terminal and an output terminal, wherein the output terminal of the output buffer circuit is configured to output a driving voltage according to a gamma voltage to a data line of a display panel in a scan line period;
a first digital-to-analog converter and a second digital-to-analog converter, wherein an output terminal of the first digital-to-analog converter is coupled to the first input terminal of the output buffer circuit and is configured to output a first gamma voltage in the scan line period, and an output terminal of the second digital-to-analog converter is coupled to the second input terminal of the output buffer circuit and is configured to output a second gamma voltage in the scan line period;
a first switch, disposed along a first signal path between the output terminal of the first digital-to-analog converter and the output terminal of the output buffer circuit; and
a second switch, disposed along a second signal path between the output terminal of the second digital-to-analog converter and the output terminal of the output buffer circuit wherein in the scan line period, only one of the first switch and the second switch is turned on, such that one of the first gamma voltage and the second gamma voltage to be output as the gamma voltage.
2. The source driver according to claim 1 , wherein
during a first scan line period, the first switch is turned on to activate the first signal path and the second switch is turned off to deactivate the second signal path, and
during a scan line second period next to the first period, the first switch is turned off to deactivate the first signal path and the second switch is turned on to activate the second signal path.
3. The source driver according to claim 2 , wherein during the first scan line period, the first digital-to-analog converter is configured to output a first gamma voltage, the first signal path is activated so as to transmit the first gamma voltage, the second digital-to-analog converter is configured to output a second gamma voltage, the second signal path is deactivated so as not to transmit the second gamma voltage, and the output buffer circuit is configured to output a driving voltage according to the first gamma voltage.
4. The source driver according to claim 2 , wherein during the second scan line period, the first digital-to-analog converter is configured to output a third gamma voltage, the first signal path is deactivated so as not to transmit the third gamma voltage, the second digital-to-analog converter is configured to output the a second gamma voltage, the second signal path is activated so as to transmit the second gamma voltage, and the output buffer circuit is configured to output a driving voltage according to the second gamma voltage.
5. The source driver according to claim 1 , wherein:
a first input data range of the first digital-to-analog converter and a second input data range of the second digital-to-analog converter are the same; and
a first output voltage range of the first digital-to-analog converter and a second output voltage range of the second digital-to-analog converter are the same.
6. The source driver according to claim 5 , further comprising:
a gamma circuit configured to provide a first gamma voltage having a first level range and a second gamma voltage having a second level range respectively to the first digital-to-analog converter and the second digital-to-analog converter, wherein the first level range is the same as the second level range.
7. The source driver according to claim 1 , wherein the first digital-to-analog converter is configured to convert a first plurality of scan lines of a frame; and the second digital-to-analog converter is configured to convert a second plurality of scan lines of the frame, wherein the first plurality of scan lines are different from the second plurality of scan lines.
8. The source driver according to claim 7 , wherein the first plurality of scan lines are odd-numbered scan lines and the second plurality of scan lines are even-numbered scan lines.
9. The source driver according to claim 1 , wherein the first scan line is a N th scan line of a frame, and the second scan line is a (N+1) th scan line of the frame.
10. The source driver according to claim 1 , wherein each of the channel circuits further comprising:
a first data latch circuit and a second data latch circuit, an output terminal of the first data latch circuit is coupled to an input terminal of the first digital-to-analog converter, and an output terminal of the second data latch circuit is coupled to an input terminal of the second digital-to-analog converter, and wherein the first data latch circuit is configured to load data according to a first loading signal indicating a first loading timing and the second data latch circuit is configured to load data according to a second loading signal indicating a second loading timing different from the first loading timing.
11. The source driver according to claim 10 , wherein a time length of a loading period for each of the first and second loading signal is twice a time length of a line latching period for each of the first data latch circuit and the second data latch circuit.
12. The source driver according to claim 10 , wherein after the first loading signal is generated to start a first latching period during which the first data latch circuit latches the first scan line of pixel data, the second loading signal is generated in the first latching period to start a second latching period during which the second data latch circuit latches a second scan line of pixel data.
13. The source driver according to claim 10 , wherein a first switching timing for the first switch depends upon the first loading timing indicated by the first loading signal and a second switching timing for the second switch depends upon the second loading timing indicated by the second loading signal.
14. The source driver according to claim 1 , wherein when one of the first digital-to-analog converter and the second digital-to-analog converter is converting pixel data for a current scan line of a frame, the other one of the first digital-to-analog converter and the second digital-to-analog converter is converting pixel data for a next scan line of a frame.