Silicide formation for source/drain contact in a vertical transport field-effect transistor

1. A method for manufacturing a semiconductor device, comprising:

forming a first vertical transistor structure in a first device region on a substrate, wherein the first vertical transistor structure comprises a first plurality of fins and a plurality of dummy source/drain regions on upper portions of the first plurality of fins;

forming a second vertical transistor structure in a second device region on the substrate, wherein the second vertical transistor structure comprises a second plurality of fins and a plurality of second source/drain regions extending from upper portions of the second plurality of fins;

forming at least one dielectric layer over the first and second vertical transistor structures;

removing a portion of the at least one dielectric layer over the first vertical transistor structure to form an opening exposing the plurality of dummy source/drain regions;

removing the plurality of dummy source/drain regions from the upper portions of the first plurality of fins via the opening to expose the upper portions of the first plurality of fins;

growing a plurality of first source/drain regions from the upper portions of the first plurality of fins;

forming a contact liner layer on the plurality of first source/drain regions;

forming a plurality of first silicide portions from the contact liner layer on the plurality of first source/drain regions;

removing another portion of the at least one dielectric layer over the second vertical transistor structure to form another opening exposing the plurality of second source/drain regions; and

forming a plurality of second silicide portions on the plurality of second source/drain regions;

wherein the plurality of second silicide portions have a different composition than the plurality of first silicide portions; and

wherein a dummy source/drain region of the plurality of dummy source/drain regions comprises an amorphous silicon layer on a dielectric layer.

2. The method according to claim 1 , wherein the plurality of first silicide portions are formed in a different silicidation step than the plurality of second silicide portions.

3. The method according to claim 1 , further comprising:

forming an additional contact liner layer on the plurality of second source/drain regions, wherein the plurality of second silicide portions are formed from the additional contact liner layer.

4. The method according to claim 3 , wherein the contact liner layer and the additional contact liner layer comprise different materials.

5. The method according to claim 1 , further comprising forming an additional contact liner layer on the plurality of first silicide portions.

6. The method according to claim 5 , wherein the contact liner layer and the additional contact liner layer comprise different materials.

7. A method for manufacturing a semiconductor device, comprising:

forming a first vertical transistor structure in a first device region on a substrate, wherein the first vertical transistor structure comprises a first plurality of fins and a plurality of dummy source/drain regions on upper portions of the first plurality of fins;

forming a second vertical transistor structure in a second device region on the substrate, wherein the second vertical transistor structure comprises a second plurality of fins and a plurality of second source/drain regions extending from upper portions of the second plurality of fins;

forming at least one dielectric layer over the first and second vertical transistor structures;

removing a portion of the at least one dielectric layer over the first vertical transistor structure to form an opening exposing the plurality of dummy source/drain regions;

removing the plurality of dummy source/drain regions from the upper portions of the first plurality of fins via the opening to expose the upper portions of the first plurality of fins;

growing a plurality of first source/drain regions from the upper portions of the first plurality of fins;

forming a contact liner layer on the plurality of first source/drain regions;

forming a plurality of first silicide portions from the contact liner layer on the plurality of first source/drain regions;

removing another portion of the at least one dielectric layer over the second vertical transistor structure to form another opening exposing the plurality of second source/drain regions;

forming a plurality of second silicide portions on the plurality of second source/drain regions;

performing an ion implantation on the exposed upper portions of the first plurality of fins;

wherein the plurality of second silicide portions have a different composition than the plurality of first silicide portions;

wherein the growing of the plurality of first source/drain regions is performed after the ion implantation;

wherein the contact liner layer is formed in the opening, and the plurality of first silicide portions are located at a bottom of the opening; and

wherein the contact liner layer is further formed on a top surface of the at least one dielectric layer adjacent the opening;

forming an organic planarization layer on the contact liner layer in the opening; and

removing the contact liner layer from the top surface of the at least one dielectric layer.

8. The method according to claim 1 , wherein the first and second device regions respectively comprise n-type and p-type transistor regions.

9. A method for manufacturing a semiconductor device, comprising:

forming a first vertical transistor structure in a first device region on a substrate, wherein the first vertical transistor structure comprises a first plurality of fins;

forming a second vertical transistor structure in a second device region on the substrate, wherein the second vertical transistor structure comprises a second plurality of fins;

growing a plurality of first source/drain regions from upper portions of the first plurality of fins;

forming a contact liner layer on the plurality of first source/drain regions;

forming a plurality of first silicide portions from the contact liner layer on the plurality of first source/drain regions;

forming a plurality of second silicide portions on a plurality of second source/drain regions extending from upper portions of the second plurality of fins;

wherein the plurality of second silicide portions have a different composition than the plurality of first silicide portions;

wherein the forming of the contact liner layer comprises:

forming at least one dielectric layer over the first and second vertical transistor structures;

removing a portion of the at least one dielectric layer over the first vertical transistor structure to form an opening; and

exposing upper portions of the first plurality of fins through the opening;

wherein the contact liner layer is formed in the opening, and the plurality of first silicide portions are located at a bottom of the opening;

wherein the contact liner layer is further formed on a top surface of the at least one dielectric layer adjacent the opening;

forming an organic planarization layer on the contact liner layer in the opening; and

removing the contact liner layer from the top surface of the at least one dielectric layer.

10. The method according to claim 9 , further comprising performing an ion implantation on the exposed upper portions of the first plurality of fins.

11. The method according to claim 10 , wherein the growing of the plurality of first source/drain regions is performed after the ion implantation.