Parasitic capacitance reduction in GaN-on-silicon devices
A method for making a semiconductor structure includes defining one or more device areas and one or more interconnect areas on a silicon substrate, forming trenches in the interconnect areas of the silicon substrate, oxidizing the silicon substrate in the trenches to form silicon dioxide regions, forming a III-nitride material layer on the surface of the silicon substrate, forming devices in the device areas of the gallium nitride layer, and forming interconnects in the interconnect areas. The silicon dioxide regions reduce parasitic capacitance between the interconnects and ground.
1. A semiconductor structure, comprising:
a silicon substrate;
at least one interconnect area, the at least one interconnect area defined by a silicon dioxide region in the silicon substrate, the silicon dioxide region being positioned between a first device area in the semiconductor structure and a second device area in the semiconductor structure;
a III-nitride material layer on a front side of the silicon substrate, the III-nitride material layer extending over the silicon substrate in the first device area, over the silicon dioxide region in the interconnect area, and over the silicon substrate in the second device area;
a first device in the III-nitride material layer in the first device area;
a second device in the III-nitride material layer in the second device area;
a metal layer on a back side of the silicon substrate; and
an interconnect over the interconnect area, the interconnect comprising a metal interconnect line that provides a continuous conductive path of metal from the first device area, over the interconnect area and the silicon dioxide region, and to the second device area.
2. The semiconductor structure as defined in claim 1 , wherein a top surface of the silicon dioxide region is coplanar with a top surface of the silicon substrate.
3. The semiconductor structure as defined in claim 1 , wherein the III-nitride material layer comprises single crystal gallium nitride.
4. The semiconductor structure as defined in claim 1 , wherein the first device and the second device comprise gallium nitride devices.
5. The semiconductor structure as defined in claim 1 , wherein the silicon dioxide region reduces parasitic capacitance between the interconnect and the metal layer on the back side of the silicon substrate in the interconnect area, as compared to a semiconductor structure in which the silicon dioxide region is not in the silicon substrate.
6. A semiconductor structure, comprising:
a silicon substrate;
a metal layer formed on a back side of the silicon substrate;
at least one interconnect area, the at least one interconnect area being defined by a silicon dioxide region in the silicon substrate, the silicon dioxide region being positioned between a first device area and a second device area in the semiconductor structure;
a III-nitride material layer formed on a front side of the silicon substrate, the III-nitride material layer extending over the silicon substrate in the first device area, over the silicon dioxide region in the interconnect area, and over the silicon substrate in the second device area;
a first device in the first device area;
a second device in the second device area; and
an interconnect comprising a continuous metal interconnect line over the interconnect area and extending continuously from the first device area, over the interconnect area and the silicon dioxide region, and to the second device area.
7. The semiconductor structure as defined in claim 6 , wherein a top surface of the silicon dioxide region is coplanar with a top surface of the silicon substrate.
8. The semiconductor structure as defined in claim 6 , wherein the III-nitride material layer comprises single crystal gallium nitride.
9. The semiconductor structure as defined in claim 6 , wherein the first device and the second device comprise gallium nitride devices.
10. The semiconductor structure as defined in claim 6 , wherein the silicon dioxide region reduces parasitic capacitance between the interconnect and the metal layer on the back side of the silicon substrate in the interconnect area, as compared to a semiconductor structure in which the silicon dioxide region is not in the silicon substrate.
11. The semiconductor structure as defined in claim 6 , wherein the silicon substrate is arranged between the metal layer and the silicon dioxide region in the semiconductor structure.
12. A semiconductor structure, comprising:
at least one interconnect area, the at least one interconnect area being defined by a low dielectric constant material region in a substrate, the low dielectric constant material region being positioned between a first device area and a second device area in the semiconductor structure;
a III-nitride material layer on a front side of the substrate, the III-nitride material layer extending over the substrate in the first device area, over the low dielectric constant material region in the interconnect area, and over the substrate in the second device area;
a first device in the first device area;
a second device in the second device area; and
an interconnect over the interconnect area, the interconnect comprising a metal interconnect line that provides a continuous conductive path of metal from the first device area, over the interconnect area and the low dielectric constant material region, and to the second device area.
13. The semiconductor structure as defined in claim 12 , wherein a top surface of the low dielectric constant material region is coplanar with a top surface of the substrate.
14. The semiconductor structure as defined in claim 12 , wherein the III-nitride material layer comprises single crystal gallium nitride.
15. The semiconductor structure as defined in claim 12 , wherein the first device and the second device comprise gallium nitride devices.
16. The semiconductor structure as defined in claim 12 , further comprising:
a metal layer on a back side of the substrate, wherein
the low dielectric constant material region reduces parasitic capacitance between the interconnect and the metal layer in the interconnect area, as compared to a semiconductor structure in which the low dielectric constant material region is not in the substrate.
17. The semiconductor structure as defined in claim 12 , wherein:
the III-nitride material layer comprises single crystal gallium nitride in the first device area and in the second device area; and
the III-nitride material layer comprises polycrystalline gallium nitride in the interconnect area.
18. The semiconductor structure as defined in claim 12 , wherein the low dielectric constant material comprises silicon dioxide.