Structure and method for gate-all-around device with extended channel

1. A method of semiconductor fabrication, comprising:

forming a semiconductor fin protruding from a substrate, the semiconductor fin including a plurality of first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked, the second semiconductor material being different from the first semiconductor material in composition;

forming a first gate stack on the semiconductor fin;

forming a recess in the semiconductor fin within a source/drain (S/D) region adjacent to the first gate stack, a sidewall of the first and second semiconductor layers being exposed within the recess;

performing an etching process to the semiconductor fin, resulting in an undercut below the first gate stack;

epitaxially growing on the sidewall of the semiconductor fin to fill in the undercut with a semiconductor extended feature of the first semiconductor material;

growing an epitaxial S/D feature from the recess;

selectively removing the second semiconductor layers; and

driving germanium into the first semiconductor layers.

2. The method of claim 1 , wherein the first semiconductor material includes silicon and the second semiconductor material includes silicon germanium.

3. The method of claim 1 , wherein the performing of the etching process includes an isotropic etching process that evenly etches the first semiconductor material and the second semiconductor material.

4. The method of claim 1 , further comprising:

forming an inter-level dielectric (ILD) layer on the S/D feature and the first gate stack;

removing the first gate stack, resulting in a gate trench; and

forming a second gate stack having a metal and a high-k dielectric material in the gate trench.

5. The method of claim 4 , wherein the selectively removing the second semiconductor layers includes selectively removing the second semiconductor layers through the gate trench before the forming of the second gate stack, and wherein the forming of the second gate stack includes forming the second gate stack surrounding the first semiconductor layers.

6. The method of claim 4 , further comprising forming a bottom contact etch stop layer (BCESL) prior to the forming of the ILD layer.

7. The method of claim 6 , wherein the forming of the ILD layer includes

depositing a dielectric material on the BCESL, the dielectric material is different from that of the BCESL in composition; and

performing a chemical mechanical polishing (CMP) process to the dielectric material.

8. A method of semiconductor fabrication, comprising:

forming a semiconductor fin protruding from a substrate, the semiconductor fin including a plurality of first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked, the second semiconductor material being different from the first semiconductor material in composition wherein the first semiconductor material includes silicon and the second semiconductor material includes silicon germanium;

forming a gate stack on the semiconductor fin;

forming a recess in the semiconductor fin within a source/drain (S/D) region adjacent to the gate stack;

performing an etching process to etch both the first and second semiconductor materials such that the semiconductor fin is laterally recessed, resulting in an undercut below the gate stack;

epitaxially growing the first semiconductor material to fill in the undercut, thereby forming an extended channel;

growing an epitaxial S/D feature in the recess;

forming an inter-level dielectric (ILD) layer on the S/D feature and the gate stack;

removing the gate stack, resulting in a gate trench;

selectively removing the second semiconductor layers through the gate trench;

driving germanium into the first semiconductor layers; and

depositing gate materials to fill in the gate trench and gaps among the first semiconductor layers, thereby forming a metal gate stack.

9. The method of claim 8 , wherein the driving germanium into the first semiconductor layers includes depositing germanium and annealing to diffuse germanium into the first semiconductor layers.

10. The method of claim 8 , wherein the gate materials include a metal and a high-k dielectric material, and wherein the metal gate stack surrounds the first semiconductor layers.

11. The method of claim 10 , wherein the forming of the metal gate stack includes depositing the high-k dielectric material such that the high-k dielectric material completely fills in the gaps among the first semiconductor layers.

12. The method of claim 11 , wherein the forming of the ILD layer includes forming a bottom contact etch-stop layer (BCESL);

depositing a dielectric material on the BCESL; and

performing a chemical mechanical polishing (CMP) process to the dielectric material, wherein the dielectric material includes a low-k dielectric material and the BCESL includes silicon nitride.

13. The method of claim 8 , wherein the growing of the epitaxial S/D feature includes epitaxially growing one of silicon, silicon germanium and silicon carbide with a first portion of a first doping concentration and a second portion of a second doping concentration on the first portion, the second doping concentration being greater than the first doping concentration.

14. A method of semiconductor fabrication, comprising:

forming a semiconductor fin protruding from a substrate, the semiconductor fin including a plurality of first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked, the second semiconductor material being different from the first semiconductor material in composition;

forming a gate structure on the semiconductor fin, the gate structure includes a dummy gate stack and a gate spacer layer;

forming a recess in the semiconductor fin within a source/drain (S/D) region adjacent to the gate structure;

performing an etching process to etch both the first and second semiconductor materials through the recess such that the first and second semiconductor layers are laterally recessed, resulting in an undercut below the gate structure;

epitaxially growing a third semiconductor material to fill in the undercut, thereby forming an extended channel;

growing an epitaxial S/D feature in the recess;

forming an inter-level dielectric (ILD) layer on the S/D feature and the gate structure;

removing the dummy gate stack, resulting in a gate trench;

selectively removing portions of the second semiconductor layers through the gate trench such that the first semiconductor layers and the extended channel are exposed within the gate trench;

performing an annealing process to remained portions of the second semiconductor layers, thereby driving germanium into the first semiconductor layers; and

depositing gate materials to fill in gaps among the first semiconductor layers, thereby forming a metal gate stack wrapping around each of the first semiconductor layers and contacting the extended channel.

15. The method of claim 14 , wherein

the growing of the epitaxial S/D feature includes epitaxially growing one of silicon, silicon germanium and silicon carbide with a first portion of a first doping concentration and a second portion of a second doping concentration on the first portion, the second doping concentration being greater than the first doping concentration;

the first and third semiconductor materials are silicon;

the second semiconductor material is silicon germanium;

the performing of the etching process includes performing an isotropic etching process that utilizes HF and/or NH 4 OH as an etchant.

16. The method of claim 8 , wherein

the selectively removing the second semiconductor layers through the gate trench includes selectively removing portions of the second semiconductor layers; and

the driving germanium into the first semiconductor layer includes performing an annealing process to remained portions of the second semiconductor layers, thereby driving germanium into the first semiconductor layers.

17. The method of claim 8 , wherein the driving germanium into the first semiconductor layer includes performing an ion implantation process to the first semiconductor layers to introduce germanium therein, after the selectively removing the second semiconductor layers through the gate trench and before the depositing gate materials to fill in gaps among the first semiconductor layers and the gate trench.

18. The method of claim 1 , wherein

the selectively removing the second semiconductor layers includes selectively removing portions of the second semiconductor layers; and

the driving germanium into the first semiconductor layer includes performing an annealing process to remained portions of the second semiconductor layers, thereby driving germanium into the first semiconductor layers.

19. The method of claim 1 , wherein the driving germanium into the first semiconductor layer includes performing an ion implantation process to the first semiconductor layers to introduce germanium therein, after the selectively removing the second semiconductor layers.

20. The method of claim 1 , wherein the driving germanium into the first semiconductor layers further include

depositing a germanium layer on the first semiconductor layers after the selectively removing the second semiconductor layers; and

performing an annealing process to drive germanium from the germanium layer into the first semiconductor layers.