Quantum well stacks for quantum dot devices
Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.
1. A quantum dot device, comprising:
a substrate, wherein the substrate includes (111) silicon;
a quantum well stack on the substrate, wherein the quantum well stack includes a quantum well layer and the quantum well layer includes (111) germanium; and
a plurality of gates above the quantum well stack, wherein the quantum well layer is between the plurality of gates and the substrate, and
wherein the quantum well stack further includes a buffer layer between the substrate and the quantum well layer and the buffer layer includes germanium tin or a group III-group V material or (111) germanium.
2. The quantum dot device of claim 1 , wherein the quantum well layer is relaxed.
3. The quantum dot device of claim 1 , wherein the quantum well layer is strained.
4. The quantum dot device of claim 1 , wherein the buffer layer further includes silicon germanium.
5. The quantum dot device of claim 4 , wherein the buffer layer further includes a second material different from silicon germanium.
6. The quantum dot device of claim 1 , wherein a germanium content of the buffer layer increases from the substrate towards the quantum well layer.
7. The quantum dot device of claim 1 , wherein the quantum well stack further includes:
a barrier layer between the buffer layer and the quantum well layer.
8. The quantum dot device of claim 7 , wherein the barrier layer is a first barrier layer, and the quantum well stack further includes:
a second barrier layer such that the quantum well layer is between the second barrier layer and the first barrier layer.
9. The quantum dot device of claim 1 , wherein at least two gates of the plurality of gates are spaced apart by spacer material.
10. A quantum dot device, comprising:
a substrate, wherein the substrate includes silicon;
a quantum well stack on the substrate, wherein the quantum well stack includes an insulating material and a quantum well layer, wherein the insulating material is between the substrate and the quantum well layer, is an oxide, has a thickness between 5 nanometers and 200 nanometers; and
a plurality of gates above the quantum well stack, wherein the quantum well layer is between the plurality of gates and the substrate.
11. The quantum dot device of claim 10 , wherein the insulating material is relaxed.
12. The quantum dot device of claim 10 , wherein the insulating material is strained.
13. The quantum dot device of claim 10 , wherein the quantum well layer includes silicon.
14. A quantum computing device, comprising:
a quantum processing device, wherein the quantum processing device includes a quantum well stack on a substrate, the quantum well stack includes a layer of an insulating material and a quantum well layer, the insulating material is between the quantum well layer and the substrate, and the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack; and
a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the plurality of gates.
15. The quantum computing device of claim 14 , further comprising:
a cooling apparatus to maintain a temperature of the quantum processing device below 5 degrees Kelvin.
16. The quantum computing device of claim 14 , wherein the insulating material includes an oxide.
17. The quantum computing device of claim 14 , wherein the insulating material is relaxed.
18. The quantum computing device of claim 14 , wherein the insulating material is strained.
19. The quantum computing device of claim 14 , wherein the quantum well layer includes silicon.