Self-interference cancellation for in-band full-duplex wireless communication

1. An in-band full-duplex transceiver with self-interference cancellation, comprising:

a self-interference correction circuit configured to vary a phase and a magnitude of a digital baseband signal to form an adjusted digital baseband signal;

a digital-to-analog converter (DAC) configured to convert the adjusted digital baseband signal into an analog self-interference cancellation signal, wherein the analog self-interference cancellation signal comprises an analog self-interference cancellation in-phase signal and an analog self-interference cancellation quadrature-phase signal;

a mixer configured to up-convert the analog self-interference cancellation signal in frequency into an up-converted analog self-interference cancellation signal, wherein the mixer comprises

an in-phase self-interference mixer configured to up-convert the analog self-interference cancellation in-phase signal responsive to a local oscillator clock signal to form an up-converted analog self-interference cancellation in-phase signal, and

a quadrature-phase self-interference mixer configured to up-convert the analog self-interference cancellation quadrature-phase signal responsive to a quadrature of the local oscillator clock signal to form an up-converted analog self-interference cancellation quadrature-phase signal, the up-converted analog self-interference cancellation signal comprising a sum of the up-converted analog self-interference cancellation in-phase signal and the up-converted analog self-interference cancellation quadrature-phase signal; and

a self-interference cancellation adder configured to add the up-converted analog self-interference cancellation signal with a received analog signal to form a self-interference-cancelled signal.

2. The in-band full-duplex transceiver of claim 1 , wherein the in-band full-duplex transceiver comprises a superheterodyne transceiver.

3. The in-band full-duplex transceiver of claim 1 , wherein the digital baseband signal comprises a digital baseband in-phase signal and digital baseband quadrature-phase signal, and wherein the self-interference correction circuit comprises:

a plurality of in-phase self-interference correction circuits each configured to adjust a phase and a magnitude of the digital baseband in-phase signal; and

a plurality of quadrature-phase self-interference correction circuits each configured to adjust a phase and a magnitude of the digital baseband quadrature-phase signal.

4. The in-band full-duplex transceiver of claim 3 , further comprising:

a first adder to add an output signal from each in-phase self-interference correction circuit to form an adjusted digital baseband in-phase signal; and

a second adder to add an output signal from each quadrature-phase self-interference correction circuit to form an adjusted digital baseband quadrature-phase signal, and wherein the DAC comprises:

a first DAC configured to convert the adjusted digital baseband in-phase signal into the analog self-interference cancellation in-phase signal; and

a second DAC configured to convert the adjusted quadrature-phase digital baseband signal into the analog self-interference cancellation quadrature-phase signal.

5. The in-band full-duplex transceiver of claim 3 , further comprising:

a radio-frequency mixer configured to down-convert a received radio-frequency signal to form the received analog signal, and wherein the received analog signal is a received intermediate-frequency signal.

6. The in-band full-duplex transceiver of claim 1 , wherein the self-interference correction circuit is configured to vary the phase and the magnitude of the digital baseband signal to form the adjusted digital baseband signal to account for a corresponding phase and a magnitude of a self-interference leakage path in the in-band-full-duplex transceiver.

7. The in-band full-duplex transceiver of claim 6 , wherein the self-interference leakage path comprises an over-the-air direct leakage path, a leakage path including a scatterer external to the in-band full-duplex transceiver; and an on-chip direct leakage path.

8. The in-band full-duplex transceiver of claim 1 , wherein the self-interference correction circuit comprises an equalizer.

9. The in-band full-duplex transceiver of claim 1 , further comprising:

a distortion circuit configured to distort the adjusted digital baseband signal responsive to non-linearities in a transmit path and in a receive path.

10. A method of reducing a self-interference in an in-band full-duplex transceiver, comprising:

adjusting a phase and a magnitude of a digital baseband signal to form an adjusted digital baseband signal to account for a leakage magnitude and a leakage phase in a leakage signal;

digital-to-analog converting the adjusted digital baseband signal into an analog self-interference cancellation signal;

frequency shifting the analog self-interference cancellation signal into an up-converted analog self-interference cancellation signal; and

adding the up-converted analog self-interference cancellation signal with a received signal to form a self-interference-cancelled received analog signal in which the leakage signal is substantially cancelled,

wherein the analog self-interference cancellation signal comprises an analog self-interference cancellation in-phase signal and an analog self-interference cancellation quadrature-phase signal, and wherein frequency shifting the analog self-interference cancellation signal comprises:

frequency shifting the analog self-interference cancellation in-phase signal into an up-converted analog self-interference cancellation in-phase signal;

frequency shifting the analog self-interference cancellation quadrature-phase signal into an up-converted analog self-interference cancellation quadrature-phase signal; and

adding the up-converted analog self-interference cancellation in-phase signal and the up-converted analog self-interference cancellation quadrature-phase signal to form the up-converted analog self-interference cancellation signal.

11. The method of claim 10 , wherein the adjusting the phase and the magnitude of the digital baseband signal comprises adjusting the digital baseband signal in an equalizer.

12. The method of claim 10 , further comprising adjusting a delay for the digital baseband signal to further reduce the self-interference in the in-band full-duplex transceiver.

13. The method of claim 10 , wherein the leakage signal is a leakage signal from an over-the-air direct leakage path for the in-band full-duplex transceiver.

14. The method of claim 10 , wherein the leakage signal is a leakage signal from a leakage path that includes an external scatterer to the in-band full-duplex transceiver.

15. The method of claim 10 , wherein the leakage signal is a leakage signal from an on-chip leakage path in the in-band full-duplex transceiver.

16. An in-band full-duplex transceiver having a self-interference leakage path, comprising:

means for adjusting a phase and a magnitude of a digital baseband signal to form an adjusted digital baseband signal;

a digital-to-analog converter (DAC) configured to convert the adjusted digital baseband signal into an analog self-interference cancellation signal, wherein the analog self-interference cancellation signal comprises an analog self-interference cancellation in-phase signal and an analog self-interference cancellation quadrature-phase signal;

a first mixer configured to up-convert the analog self-interference cancellation signal in frequency into an up-converted analog self-interference cancellation signal, wherein the first mixer comprises

an in-phase self-interference mixer configured to up-convert the analog self-interference cancellation in-phase signal responsive to a local oscillator clock signal to form an up-converted analog self-interference cancellation in-phase signal, and

a quadrature-phase self-interference mixer configured to up-convert the analog self-interference cancellation quadrature-phase signal responsive to a quadrature of the local oscillator clock signal to form an up-converted analog self-interference cancellation quadrature-phase signal, the up-converted analog self-interference cancellation signal comprising a sum of the up-converted analog self-interference cancellation in-phase signal and the up-converted analog self-interference cancellation quadrature-phase signal; and

a self-interference cancellation adder configured to add the up-converted analog self-interference cancellation signal with a received analog signal to form a self-interference-cancelled signal.

17. The in-band full-duplex transceiver of claim 16 , further comprising:

a second mixer configured to down-convert the self-interference-cancelled signal into a baseband signal.

18. The in-band full-duplex transceiver of claim 16 , wherein the means comprises an equalizer.

19. The in-band full-duplex transceiver of claim 16 , wherein the DAC comprises an in-phase DAC and a quadrature-phase DAC.

20. The in-band full-duplex transceiver of claim 19 , wherein the self-interference correction circuit comprises a plurality of in-phase self-interference correction circuits and a plurality of quadrature-phase self-interference correction circuits, wherein the adjusted digital baseband signal comprises an adjusted digital baseband in-phase signal and an adjusted digital baseband quadrature-phase signal, the adjusted digital baseband in-phase signal comprising a summation of outputs of the plurality of in-phase self-interference correction circuits, the adjusted digital baseband quadrature-phase signal comprising a summation of outputs of the plurality of quadrature-phase self-interference correction circuits, wherein the in-phase DAC is configured to convert the adjusted digital baseband in-phase signal into the analog self-interference cancellation in-phase signal, and wherein the quadrature-phase DAC is configured to convert the adjusted digital baseband quadrature-phase signal into the analog self-interference cancellation quadrature-phase signal.