IP Library Granted Patent US 11,159,752
Granted Patent B2
US 11,159,752 · App. 16/815,257 · Granted Oct 26, 2021

Imaging device

Inventors: Yutaka Abe (Osaka, JP); Kazuko Nishimura (Kyoto, JP); Masashi Murakami (Kyoto, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H04N5/353H04N5/357H04N5/363
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Quick Facts
Patent No.
US 11,159,752
App. No.
16/815,257
Granted
Oct 26, 2021
Kind
B2
Abstract

An imaging device includes a photoelectric converter that converts light into signal charge, a charge accumulation region that accumulates the signal charge, a first transistor having a gate connected to the charge accumulation region, and a common gate amplifier circuit that amplifies an output of the first transistor to output to the charge accumulation region. The common gate amplifier circuit includes a second transistor. One of a source and a drain of the second transistor is connected to one of a source and a drain of the first transistor, and the other of the source and the drain of the second transistor is connected to the charge accumulation region.

Claims (39)

1. An imaging device comprising:

a photoelectric converter that converts light into signal charge;

a charge accumulation region that accumulates the signal charge;

a first transistor having a gate connected to the charge accumulation region; and

a common gate amplifier circuit that amplifies an output of the first transistor to output to the charge accumulation region,

wherein the common gate amplifier circuit includes a second transistor, and

wherein one of a source and a drain of the second transistor is connected to one of a source and a drain of the first transistor, and the other of the source and the drain of the second transistor is connected to the charge accumulation region.

2. The imaging device according to claim 1 , wherein the common gate amplifier circuit has a voltage gain greater than 1 in a first period.

3. The imaging device according to claim 1 , wherein the common gate amplifier circuit has a voltage gain greater than 1 in a first period and has a voltage gain greater than or equal to 0 and less than or equal to 1 in a second period.

4. The imaging device according to claim 1 , further comprising:

a first voltage supply circuit that is connected to the other of a source and a drain of the first transistor and that selectively outputs at least two types of different voltages; and

a second voltage supply circuit that is connected to a gate of the second transistor and that selectively outputs at least three types of different voltages.

5. The imaging device according to claim 4 , wherein the at least three types of voltages output from the second voltage supply circuit include a voltage that causes the second transistor to operate in a saturation region.

6. The imaging device according to claim 1 , further comprising:

a current supplier including a first current supply and a second current supply,

wherein the current supplier selectively connects one of the first current supply and the second current supply to the one of the source and drain of the second transistor.

7. The imaging device according to claim 1 , further comprising:

a current supply connected to a node between the one of the source and drain of the first transistor and the one of the source and drain of the second transistor without using a switching element between the current supply and the node.

8. The imaging device according to claim 1 , further comprising:

a first current supply configured to be connected to the one of the source and drain of the first transistor; and

a second current supply configured to be connected to the other of the source and drain of the first transistor,

wherein one of the first current supply and the second current supply is electrically connected to the first transistor, and

wherein a direction of a current flowing in the first transistor when the first current supply is electrically connected to the first transistor is the same as a direction of a current flowing in the first transistor when the second current supply is electrically connected to the first transistor.

9. The imaging device according to claim 1 , further comprising:

a differential amplifier circuit having a first input terminal, a second input terminal, and an output terminal, the first input terminal being connected to the one of the source and drain of the first transistor, the output terminal being connected to the one of the source and drain of the second transistor;

a first voltage supply circuit connected to the second input terminal, the first voltage supply circuit selectively outputting at least two types of different voltages; and

a second voltage supply circuit connected to a gate of the second transistor, the second voltage supply circuit selectively outputting at least three types of different voltages.

10. The imaging device according to claim 9 , wherein the at least three types of voltages output from the second voltage supply circuit include a voltage that causes the second transistor to operate in a saturation region.

11. The imaging device according to claim 1 , further comprising:

a first capacitor having a first terminal and a second terminal, the first terminal being connected to the other of the source and drain of the second transistor; and

a second capacitor having a third terminal and a fourth terminal, the third terminal being connected to the charge accumulation region, the fourth terminal being connected to the first terminal.

12. The imaging device according to claim 11 , wherein a capacitance of the first capacitor is larger than a capacitance of the second capacitor.

13. The imaging device according to claim 11 , further comprising:

a third voltage supply circuit connected to the second terminal, the third voltage supply circuit outputting a voltage that varies with time.

14. The imaging device according to claim 11 , further comprising:

a third transistor having one of a source and a drain connected to the third terminal and the other of the source and the drain connected to the fourth terminal.

15. The imaging device according to claim 1 , further comprising:

a bias transistor having one of a source and a drain connected to the other of the source and drain of the second transistor; and

a bias voltage supply connected to the other of the source and the drain of the bias transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2020
From: ABE, YUTAKA; NISHIMURA, KAZUKO; MURAKAMI, MASASHI
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 052740/0489 →
Priority Claims (1)
JP JP2019-053883 · Mar 20, 2019 · national
Continuity (1)
Related Publication 20200304735A1 · Sep 24, 2020