Distribution-following access operations for a memory device
Methods, systems, and devices for distribution-following access operations for a memory device are described. In an example, the described techniques may include identifying an activation of a first memory cell at a first condition of a biasing operation, and identifying an activation of a second memory cell at a second condition of the biasing operation, and determining a parameter of an access operation based at least in part on a difference between the first condition and the second condition. In some examples, the memory cells may be associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time.
1. An apparatus, comprising:
a set of memory cells; and
circuitry coupled with the set of memory cells and configured to:
initiate a biasing operation on the set of memory cells;
identify, at a first condition of the biasing operation, switching of a first quantity of the set of memory cells;
identify, at a second condition of the biasing operation, switching of a second quantity of the set of memory cells; and
determine a parameter of an access operation based at least in part on a difference between the first condition and the second condition.
2. The apparatus of claim 1 , wherein the first condition corresponds to a first time of the biasing operation and the second condition corresponds to a second time of the biasing operation, and to determine the parameter of the access operation, the circuitry is configured to:
determine a duration of the biasing operation based at least in part on a difference between the first time and the second time.
3. The apparatus of claim 1 , wherein the first condition corresponds to a first voltage of the biasing operation and the second condition corresponds to a second voltage of the biasing operation, and to determine the parameter of the access operation, the circuitry is configured to:
determine a voltage of the access operation based at least in part on a difference between the first voltage and the second voltage.
4. The apparatus of claim 1 , wherein the circuitry is configured to:
write the set of memory cells with a third quantity of the set of memory cells having a first logic state and a fourth quantity of the set of memory cells having a second logic state, wherein the circuitry is configured to identify switching of the first quantity of the set of memory cells and identify switching of the second quantity of the set of memory cells based at least in part on the third quantity of the set of memory cells.
5. The apparatus of claim 1 , wherein, to perform the biasing operation, the circuitry is configured to:
bias the set of memory cells with a voltage that increases over the biasing operation.
6. The apparatus of claim 1 , wherein the access operation comprises the biasing operation, the first condition comprises a first voltage of the biasing operation, and the second condition comprises a second voltage of the biasing operation, and to determine the parameter of the access operation, the circuitry is configured to:
determine a reference voltage of the access operation based at least in part on a difference between the first voltage and the second voltage.
7. The apparatus of claim 1 , wherein the access operation comprises the biasing operation, the first condition comprises a first time of the biasing operation, and the second condition comprises a second time of the biasing operation, and to determine the parameter of the access operation, the circuitry is configured to:
determine a completion time of the access operation based at least in part on a difference between the first time and the second time.
8. The apparatus of claim 1 , wherein the circuitry is configured to:
modify the access operation based at least in part on the determined parameter.
9. The apparatus of claim 2 , wherein, to determine the duration of the access operation, the circuitry is configured to:
determine the duration based at least in part on an average of the first time and the second time and the difference between the first time and the second time.
10. The apparatus of claim 2 , wherein, to determine the duration of the access operation, the circuitry is configured to:
determine the duration based at least in part on the second time and the difference between the first time and the second time.
11. The apparatus of claim 3 , wherein to determine the voltage for evaluation of the access operation, the circuitry is configured to:
determine the voltage for evaluation of the access operation based at least in part on the second voltage and the difference between the first voltage and the second voltage.
12. The apparatus of claim 3 , wherein to determine the voltage for evaluation of the access operation, the circuitry is configured to:
determine the voltage for evaluation of the access operation based at least in part on an average of the first voltage and the second voltage and the difference between the first voltage and the second voltage.
13. The apparatus of claim 1 , wherein the circuitry is configured to:
identify switching of the first quantity of the set of memory cells based at least in part on determining that the biasing operation has caused a respective switching event at each of the first quantity of the set of memory cells of the set of memory cells; and
identify switching of the second quantity of the set of memory cells based at least in part on determining that the biasing operation has caused a respective switching event at each of the second quantity of the set of memory cells of the set of memory cells.
14. The apparatus of claim 1 , wherein to identify switching of the first quantity of the set of memory cells, to identify switching of the second quantity of the set of memory cells, or both, the circuitry is configured to:
identify a thresholding of the respective quantity of the set of memory cells.
15. The apparatus of claim 1 , wherein to identify switching of the first quantity of the set of memory cells, to identify switching of the second quantity of the set of memory cells, or both, the circuitry is configured to:
identify a change of resistance of the respective quantity of the set of memory cells.
16. A method, comprising:
initiating a biasing operation on a set of memory cells;
identifying a first condition of the biasing operation corresponding to switching of a first quantity of memory cells of the set of memory cells;
identifying a second condition of the biasing operation corresponding to switching of a second quantity of memory cells of the set of memory cells; and
determining a parameter of an access operation based at least in part on a difference between the first condition and the second condition.
17. The method of claim 16 , wherein the access operation comprises the biasing operation, and wherein determining the parameter of the access operation comprises:
determining a condition for ending the biasing operation.
18. The method of claim 17 , wherein determining condition for ending the biasing operation comprises:
determining an end time of the biasing operation.
19. The method of claim 17 , wherein determining the condition for ending the biasing operation comprises:
determining an end voltage of the biasing operation.
20. The method of claim 16 , further comprising:
modifying the access operation based at least in part on the determined parameter.
21. The method of claim 16 , wherein the first condition corresponds to a first time of the biasing operation and the second condition corresponds to a second time of the biasing operation, and determining the parameter comprises:
determining a duration of the access operation based at least in part on a difference between the first time and the second time.
22. The method of claim 16 , wherein the first condition corresponds to a first voltage of the biasing operation and the second condition corresponds to a second voltage of the biasing operation, and wherein determining the parameter comprises:
determining a voltage for evaluation of the access operation based at least in part on a difference between the first voltage and the second voltage.
23. The method of claim 16 , wherein the biasing operation comprises:
biasing the set of memory cells with a voltage that increases over the biasing operation.
24. The method of claim 16 , wherein the access operation comprises the biasing operation, the first condition comprises a first voltage of the biasing operation, and the second condition comprises a second voltage of the biasing operation, and determining the parameter of the access operation comprises:
determining a reference voltage of the access operation based at least in part on a difference between the first voltage and the second voltage.
25. The method of claim 16 , wherein identifying the first condition of the biasing operation is based at least in part on identifying a thresholding of memory cells of the first quantity of memory cells, or wherein identifying the second condition of the biasing operation is based at least in part on identifying a thresholding of memory cells of the second quantity of memory cells, or both.
26. The method of claim 16 , wherein identifying the first condition of the biasing operation is based at least in part on identifying a change of resistance of memory cells of the first quantity of memory cells, or wherein identifying the second condition of the biasing operation is based at least in part on identifying a change of resistance of memory cells of the second quantity of memory cells, or both.